ADSP-2183KCA-210 Analog Devices Inc, ADSP-2183KCA-210 Datasheet - Page 14
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ADSP-2183KCA-210
Manufacturer Part Number
ADSP-2183KCA-210
Description
Digital Signal Processor(DSP) IC
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2183BSTZ-160.pdf
(31 pages)
Specifications of ADSP-2183KCA-210
Rohs Status
RoHS non-compliant
Interface
Synchronous Serial Port (SSP)
Clock Rate
52MHz
Non-volatile Memory
External
On-chip Ram
80kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-MBGA, 144-Mini-BGA
Device Core Size
16b
Format
Fixed Point
Clock Freq (max)
52MHz
Mips
52
Device Input Clock Speed
52MHz
Ram Size
80KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
CSPBGA
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-2183KCA-210
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-2183KCA-210
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-2183
Parameter
Clock Signals and Reset
Timing Requirements:
t
t
t
Switching Characteristics:
t
t
t
Control Signals
Timing Requirement:
t
NOTE
1
Parameter
Interrupts and Flag
Timing Requirements:
t
t
Switching Characteristics:
t
t
NOTES
1
2
3
4
5
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
If IRQx and FI inputs meet t
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
CKI
CKIL
CKIH
CKL
CKH
CKOH
RSP
oscillator start-up time).
IFS
IFH
FOH
FOD
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
RESET Width Low
IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
IFS
CLKOUT
and t
CLKIN
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
OUTPUTS
CLKOUT
FLAG
IRQx
PFx
FI
t
CKIL
5
t
CKI
5
t
t
FOH
FOD
t
CKL
1, 2, 3, 4
1, 2, 3, 4
t
IFH
Min
38
15
15
0.5t
0.5t
0
5t
t
CK
CKOH
t
Min
0.25t
0.25t
0.5t
CKH
CK
CK
t
1
IFS
– 7
– 7
CK
t
CKIH
CK
CK
– 7
+ 15
Max
0.5t
Max
100
20
CK
+ 6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit