ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 18

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 7. Signal Descriptions
Signal Name
PF8/MDC/PPI D8/SPI1SEL4
PF9/MDIO/PPI D9/TMR2
PF10/ETxD0/PPI D10/TMR3
PF11/ERxD0/PPI D11/PWM AH/TACI3
PF12/ETxD1/PPI D12/PWM AL
PF13/ERxD1/PPI D13/PWM BH
PF14/ETxEN/PPI D14/PWM BL
PF15
Port G: GPIO and Multiplexed Peripherals
PG0/MIICRS/RMIICRS/HWAIT
PG1/ERxER/DMAR1/PWM CH
PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O
PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3
PG4/RSCLK0/RSI_DATA1/TMR5/TACI5
PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK
PG6/TFS0/RSI_DATA3/TMR0/PPIFS1
PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2
PG8/TSCLK0/RSI_CLK/TMR6/TACI6
PG9/DT0SEC/UART0TX/TMR4
PG10/DR0SEC/UART0RX/TACI4
PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2
PG12/SPI0SCK/PPICLK/TMRCLK/PTP_PPS
PG13/SPI0MISO
PTP_CLKOUT
PG14/SPI0MOSI/TMR1/PPIFS2/PWM TRIP
/PTP_AUXIN
PG15/SPI0SEL2/PPIFS3/AMS3
Port H: GPIO and Multiplexed Peripherals
PH0/DR1PRI/SPI1SS/RSI_DATA4
PH1/RFS1/SPI1MISO/RSI_DATA5
PH2/RSCLK1/SPI1SCK/RSI DATA6
PH3/DT1PRI/SPI1MOSI/RSI DATA7
PH4/TFS1/AOE/SPI0SEL3/CUD
PH5/TSCLK1/ARDY/PTP_EXT_CLKIN/CDG
PH6/DT1SEC/UART1TX/SPI1SEL1/CZM
PH7/DR1SEC/UART1RX/TMR7/TACI2
2
/RMII PHYINT/PPI D15/PWM_SYNCA
4
/TMR0/PPIFS1/
3
/SPI1SEL3
Type Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Rev. B | Page 18 of 68 | January 2011
GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4
GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2
GPIO/Ethernet MII or RMII Transmit D0/PPI Data 10/Timer 3
GPIO/Ethernet MII Receive D0/PPI Data 11/PWM AH output
/Timer3 Alternate Capture Input
GPIO/Ethernet MII Transmit D1/PPI Data 12/PWM AL Output
GPIO/Ethernet MII or RMII Receive D1/PPI Data 13/PWM BH Output
GPIO/Ethernet MII Transmit Enable/PPI Data 14/PWM BL Out
GPIO/Ethernet MII PHY Interrupt/PPI Data 15/Alternate PWM Sync
GPIO/Ethernet MII or RMII Carrier Sense or RMII Data Valid/HWAIT/SPI1 Slave Select3 C
GPIO/Ethernet MII or RMII Receive Error/DMA Req 1/PWM CH Out
GPIO/Ethernet MII or RMII Reference Clock/DMA Req 0/PWM CL Out
GPIO/SPORT0 Primary Rx Data/RSI Data 0/SPI0 Slave Select 5/Timer3 Alternate CLK C
GPIO/SPORT0 Rx Clock/RSI Data 1/Timer 5/Timer5 Alternate Capture Input
GPIO/SPORT0 Rx Frame Sync/RSI Data 2/PPI Clock/External Timer Reference
GPIO/SPORT0 Tx Frame Sync/RSI Data 3/Timer0/PPI Frame Sync1
GPIO/SPORT0 Tx Primary Data/RSI Command/Timer 1/PPI Frame Sync2
GPIO/SPORT0 Tx Clock/RSI Clock/Timer 6/Timer6 Alternate Capture Input
GPIO/SPORT0 Secondary Tx Data/UART0 Transmit/Timer 4
GPIO/SPORT0 Secondary Rx Data/UART0 Receive/Timer4 Alternate Capture Input C
GPIO/SPI0 Slave Device Select/Asynchronous Memory Bank Select 2/SPI1 Slave
Select 5/Timer2 Alternate CLK
GPIO/SPI0 Clock/PPI Clock/External Timer Reference/PTP Pulse Per Second Out
GPIO/SPI0 Master In Slave Out/Timer0/PPI Frame Sync1/PTP Clock Out
GPIO/SPI0 Master Out Slave In/Timer 1/PPI Frame Sync2/PWM Trip/PTP Auxiliary
Snapshot Trigger Input
GPIO/SPI0 Slave Select 2/PPI Frame Sync3/Asynchronous Memory Bank Select 3
GPIO/SPORT1 Primary Rx Data/SPI1 Device Select/RSI Data 4
GPIO/SPORT1 Rx Frame Sync/SPI1 Master In Slave Out/RSI Data 5
GPIO/SPORT1 Rx Clock/SPI1 Clock/RSI Data 6
GPIO/SPORT1 Primary Tx Data/SPI1 Master Out Slave In/RSI Data 7
GPIO/SPORT1 Tx Frame Sync/Asynchronous Memory Output Enable/SPI0 Slave
Select 3/Counter Up Direction
GPIO/SPORT1 Tx Clock/Asynchronous Memory Hardware Ready Control/
External Clock for PTP TSYNC/Counter Down Gate
GPIO/SPORT1 Secondary Tx Data/UART1 Transmit/SPI1 Slave Select 1
/Counter Zero Marker
GPIO/SPORT1 Secondary Rx Data/UART1 Receive/Timer 7/Timer2 Alternate Clock
Input
Driver
Type
C
C
C
C
C
C
C
C
C
C
D
C
C
C
D
C
C
D
C
C
C
C
C
D
C
C
D
C
C
1