ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 45

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Up/Down Counter/Rotary Encoder Timing
Table 42. Up/Down Counter/Rotary Encoder Timing
1
10/100 Ethernet MAC Controller Timing
Table 43
describe the 10/100 Ethernet MAC Controller operations.
Table 43. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
1
Parameter
Timing Requirements
t
t
t
t
Parameter
Timing Requirements
t
t
t
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
ERXCLKF
ERXCLKW
ERXCLKIS
ERXCLKIH
WCOUNT
CIS
CIH
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
through
Up/Down Counter/Rotary Encoder Input Pulse Width
Counter Input Setup Time Before CLKOUT Low
Counter Input Hold Time After CLKOUT Low
1
ERxCLK Frequency (f
ERxCLK Width (t
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
Table 48
ERx_CLK
ERxD3–0
ERxDV
ERxER
and
CUD/CDG/CZM
ERxCLK
Figure 31
CLKOUT
SCLK
= ERxCLK Period)
= SCLK Frequency)
Figure 31. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
t
through
ERXCLKIS
Figure 30. Up/Down Counter/Rotary Encoder Timing
Figure 36
t
ERXCLKIH
Rev. B | Page 45 of 68 | January 2011
1
t
ERXCLKW
1
t
CIS
t
WCOUNT
Min
None
t
7.5
7.5
t
ERxCLK
ERXCLK
x 40%
t
CIH
1.8V Nominal
V
DDEXT
Max
25 + 1%
t
ERxCLK
x 60%
Min
t
9
0
SCLK
1.8V Nominal
+ 1
V
DDEXT
Max
Min
None
t
7.5
7.5
ERxCLK
2.5 V/3.3V Nominal
x 35%
Min
t
7
0
2.5 V/3.3V Nominal
SCLK
V
DDEXT
+ 1
Max
25 + 1%
t
ERxCLK
V
DDEXT
Max
x 65%
Unit
MHz
ns
ns
ns
Unit
ns
ns
ns