ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 27

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Clock and Reset Timing
Table 23
the CCLK and SCLK timing specifications in
and
multipliers must not select core/peripheral clocks in excess of
the processor’s speed grade.
Table 23. Clock and Reset Timing
1
2
3
4
5
Table 24. Power-Up Reset Timing
Parameter
Timing Requirements
t
Parameter
Timing Requirements
f
f
t
t
t
Switching Characteristic
t
Applies to PLL bypass mode and PLL nonbypass mode.
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
The t
If the DF bit in the PLL_CTL register is set, the minimum f
Applies after power-up sequence is complete. See
RST_IN_PWR
CKIN
CKIN
CKINL
CKINH
WRST
BUFDLAY
Table 11 on Page
CKIN
period (see
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
and
RESET Deasserted after the V
Stable and Within Specification
Figure 7
CLKBUF
Figure
CLKIN
CLKIN Frequency (Commercial/Industrial Models
CLKIN Frequency (Automotive Models)
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
CLKIN to CLKBUF Delay
21, combinations of CLKIN and clock
describe clock and reset operations. Per
7) equals 1/f
t
CKINL
CKIN
1
.
1
t
CKIN
Table 24
DDINT
t
CKINH
, V
Table 9
DDEXT
CKIN
and
, V
Rev. B | Page 27 of 68 | January 2011
specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
Figure 8
DDRTC
5
,
Table
, V
Figure 7. Clock and Reset Timing
t
WRST
DDMEM
1, 2, 3, 4
for power-up reset timing.
10,
, V
DDOTP
, and CLKIN Pins are
1, 2, 3, 4
Min
12
14
10
10
11 × t
VCO
, f
CKIN
CCLK
, and f
t
BUFDLAY
SCLK
Min
3500 × t
settings discussed in
CKIN
Max
50
50
11
Table 9
Max
t
BUFDLAY
through
Table 11 on Page
Unit
ns
Unit
MHz
MHz
ns
ns
ns
ns
21.