ADSP-BF526KBCZ-3 Analog Devices Inc, ADSP-BF526KBCZ-3 Datasheet - Page 17

• Manufacturer Part Number: ADSP-BF526KBCZ-3
• Description: ADSP-BF526 Processor,300Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF526KBCZ-3

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 300MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on
“EE-168.”
The CLKBUF pin is an output pin, which is a buffered version
of the input clock. This pin is particularly useful in Ethernet
applications to limit the number of required clock sources in the
system. In this type of application, a single 25 MHz or 50 MHz
crystal may be applied directly to the processor. The 25 MHz or
50 MHz output of CLKBUF can then be connected to an exter-
nal Ethernet MII or RMII PHY device. If, instead of a crystal, an
external oscillator is used at CLKIN, CLKBUF will not have the
40/60 duty cycle required by some devices. The CLKBUF output
is active by default and can be disabled for power savings rea-
sons using the VR_CTL register.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable multiplication factor
(bounded by specified minimum and maximum VCO frequen-
cies). The default multiplier can be modified by a software
instruction sequence. This sequence is managed by the
bfrom_SysControl() function in the on-chip ROM.
On-the-fly CCLK and SCLK frequency changes can be applied
by using the bfrom_SysControl() function in the on-chip ROM.
The maximum allowed CCLK and SCLK rates depend on the
applied voltages V
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
CLKOUT
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0
CLKBUF
Figure
Figure 6. External Crystal Connections
6. A design procedure for third-overtone oper-
EN
EN
DDINT
, V
CLKIN
Figure
18 pF *
BLACKFIN
DDEXT
, and V
330
TO PLL CIRCUITRY
7, the core clock (CCLK) and
*
DDMEM
560
XTAL
18 pF *
.
FOR OVERTONE
OPERATION ONLY:
; the VCO is always
Rev. B | Page 17 of 88 | May 2010
permitted to run up to the frequency specified by the part’s
maximum instruction rate. The CLKOUT pin reflects the SCLK
frequency to the off-chip world. It is part of the SDRAM inter-
face, but it functions as a reference signal in other timing
specifications as well. While active by default, it can be disabled
using the EBIU_SDGCTL and EBIU_AMGCTL registers.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
dynamically changed without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV)
using the bfrom_SysControl() function in the on-chip ROM.
Table 6. Example System Clock Ratios
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name
SSEL3–0
0001
0110
1010
Signal Name
CSEL1–0
00
01
10
11
Table 6
CLKIN
7. This programmable core clock capability is useful for
REQUIRES PLL SEQUENCING
illustrates typical system clock ratios.
“FINE” ADJUSTMENT
Figure 7. Frequency Modification Methods
5u to 64u
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
PLL
SCLK d CCLK
VCO
VCO
300
300
500
200
VCO
100
300
500
Example Frequency Ratios
Example Frequency Ratios
SCLK
. The SSEL value can be
“COARSE” ADJUSTMENT
÷ 1 to 15
÷ 1, 2, 4, 8
(MHz)
(MHz)
ON-THE-FLY
SCLK
100
50
50
CCLK
300
150
125
25
CCLK
SCLK