ADSP-BF526KBCZ-3 Analog Devices Inc, ADSP-BF526KBCZ-3 Datasheet - Page 75

• Manufacturer Part Number: ADSP-BF526KBCZ-3
• Description: ADSP-BF526 Processor,300Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF526KBCZ-3

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 300MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Disable Time Measurement
Output balls are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
difference between t
side of
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load C
time can be approximated by the equation:
The time t
ΔV equal to 0.25 V for V
and 0.15 V for V
The time t
signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. C
the total bus capacitance (per data line), and I
age or three-state current (per data line). The hold time will be
t
Timing Specifications on Page 38
SDRAM write cycle as shown in
Page
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see
to (V
Figure 72
The delay and hold specifications given should be derated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
DECAY
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
DDEXT
46).
plus the various output disable times as specified in the
Figure
show how output rise time varies with capacitance.
DECAY
DIS_MEASURED
/V
DDMEM
t
59.
DIS
DECAY
is calculated with test loads C
DDEXT
=
) /2. The graphs of
DIS_MEASURED
t
using the equation given above. Choose ΔV
DECAY
t
/V
DIS_MEASURED
is the interval from when the reference
L
DDMEM
DDEXT
and the load current I
=
/V
(nominal) = 1.8V.
(
and t
DDMEM
SDRAM Interface Timing on
C
(for example t
L
Δ
–
Figure
V
DECAY
Figure 61
t
(nominal) = 2.5 V/3.3 V
) I
DECAY
⁄
L
as shown on the left
60). V
L
L
and I
is the total leak-
L
. This decay
DSDAT
through
LOAD
L
Rev. B | Page 75 of 88 | May 2010
, and with
DIS
for an
is equal
is the
L
is
V
LOAD
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
4pF
Figure 61. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Figure 60. Equivalent Device Loading for AC Measurements
12
10
8
6
4
2
0
50Ω
0
70Ω
50Ω
400Ω
2pF
Load Capacitance (1.8V V
50
(Includes All Fixtures)
45Ω
0.5pF
TESTER PIN ELECTRONICS
LOAD CAPACITANCE (pF)
100
ZO = 50Ω (impedance)
TD = 4.04 ± 1.18 ns
DDEXT
/V
T1
150
DDMEM
t
t
t
)
RISE
RISE
FALL
t
FALL
= 1.8V @ 25
= 1.8V @ 25
OUTPUT
200
DUT
° C
° C