ADSP-BF527BBCZ-5A Analog Devices Inc, ADSP-BF527BBCZ-5A Datasheet - Page 53
![ADSP-BF527 Processor,533Mhz,Ethernet,USB](/photos/6/71/67135/bc-289-2_sml.jpg)
ADSP-BF527BBCZ-5A
Manufacturer Part Number
ADSP-BF527BBCZ-5A
Description
ADSP-BF527 Processor,533Mhz,Ethernet,USB
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Specifications of ADSP-BF527BBCZ-5A
Interface
DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
Clock Rate
533MHz
Non-volatile Memory
ROM (32 kB)
On-chip Ram
132kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.15V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF527BBCZ-5A
Manufacturer:
ADI
Quantity:
190
Company:
Part Number:
ADSP-BF527BBCZ-5A
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-BF527BBCZ-5A
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Table 43. Serial Ports—Internal Clock for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
1
2
Table 44. Serial Ports—Internal Clock for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
1
2
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Referenced to sample edge.
Referenced to drive edge.
SFSI
HFSI
SDRI
HDRI
SCLKIW
DFSI
HOFSI
DDTI
HDTI
SFSI
HFSI
SDRI
HDRI
SCLKIW
DFSI
HOFSI
DDTI
HDTI
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
1
2
2
1
1
1
1
2
2
2
Rev. B | Page 53 of 88 | May 2010
2
1
1
1
Min
11.0
–1.5
11.0
–1.5
4.5
−1.0
−1.8
1.8V Nominal
2
2
Min
11.0
–1.5
11.0
–1.5
10.0
−2.0
−1.8
V
DDEXT
1.8V Nominal
Max
3.0
3.0
V
DDEXT
Max
3.0
3.0
Min
9.6
–1.5
9.6
–1.5
4.5
−1.0
−1.5
Min
9.6
–1.5
9.6
–1.5
8.0
−1.0
−1.5
2.5/3.3V Nominal
2.5/3.3V Nominal
V
V
DDEXT
DDEXT
Max
3.0
3.0
Max
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns