ADSP-BF527BBCZ-5A Analog Devices Inc, ADSP-BF527BBCZ-5A Datasheet - Page 67
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ADSP-BF527BBCZ-5A
Manufacturer Part Number
ADSP-BF527BBCZ-5A
Description
ADSP-BF527 Processor,533Mhz,Ethernet,USB
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Specifications of ADSP-BF527BBCZ-5A
Interface
DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
Clock Rate
533MHz
Non-volatile Memory
ROM (32 kB)
On-chip Ram
132kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.15V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF527BBCZ-5A
Manufacturer:
ADI
Quantity:
190
Company:
Part Number:
ADSP-BF527BBCZ-5A
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-BF527BBCZ-5A
Manufacturer:
ADI/亚德诺
Quantity:
20 000
10/100 Ethernet MAC Controller Timing
Table 57
describe the 10/100 Ethernet MAC Controller operations.
Table 57. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
1
Table 58. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
1
Parameter
Timing Requirements
t
t
t
t
Parameter
Switching Characteristics
t
t
t
t
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
MII outputs synchronous to ETxCLK are ETxD3–0.
ERXCLKF
ERXCLKW
ERXCLKIS
ERXCLKIH
ETXCLKF
ETXCLKW
ETXCLKOV
ETXCLKOH
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
through
1
1
Table 62
ERxCLK Frequency (f
ERxCLK Width (t
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5
ETxCLK Frequency (f
ETxCLK Width (t
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out
Hold)
ERx_CLK
ERxD3–0
ERxDV
ERxER
and
Figure 36
MIITxCLK
ETxCLK
ETxD3–0
ERxCLK
ETxEN
Figure 37. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
SCLK
SCLK
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
= ETxCLK Period)
= ERxCLK Period)
through
t
ERXCLKIS
= SCLK Frequency)
= SCLK Frequency)
Figure 41
t
ERXCLKIH
Rev. B | Page 67 of 88 | May 2010
t
t
ETXCLKOH
ERXCLKW
t
ETXCLKW
t
ETXCLKOV
t
ERXCLK
t
ETXCLK
Min
None
t
7.5
Min
None
t
0
ERxCLK
ETxCLK
× 40% t
× 40% t
1.8V Nominal
1.8V Nominal
V
V
DDEXT
DDEXT
Max
25 + 1%
Max
25 + 1%
20
ERxCLK
ETxCLK
× 60% t
× 60% t
Min
None
7.5
7.5
Min
None
0
ERxCLK
ETxCLK
2.5/3.3V Nominal
2.5/3.3V Nominal
× 35% t
× 35% t
V
V
DDEXT
DDEXT
Max
25 + 1%
Max
25 + 1%
20
ERxCLK
ETxCLK
× 65% ns
× 65% ns
Unit
MHz
ns
ns
Unit
MHz
ns
ns