ADUC7128BCPZ126-RL Analog Devices Inc, ADUC7128BCPZ126-RL Datasheet - Page 13
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ADUC7128BCPZ126-RL
Manufacturer Part Number
ADUC7128BCPZ126-RL
Description
IC,MICROCONTROLLER,16-BIT,ARM7 CPU,LLCC,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7128QSPZ.pdf
(92 pages)
Specifications of ADUC7128BCPZ126-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
41.78MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
PLA, POR, PWM, PSM, Temp Sensor, WDT
Number Of I /o
28
Program Memory Size
126KB (126K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x12b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADUC7128BCPZ126-RLTR
Table 7. SPI Slave Mode Timing (PHASE Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
2
CS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SFS
t
t
UCLK
HCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
depends on the clock divider or CD bits in the PLLCON MMR, t
(POLARITY = 0)
(POLARITY = 1)
SCLOCK
SCLOCK
Description
CS to SCLOCK edge
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
CS high after SCLOCK edge
MISO
MOSI
CS
t
CS
1
t
t
DSU
DAV
2
2
t
SH
Figure 8. SPI Slave Mode Timing (PHASE Mode = 1)
MSB IN
HCLK
t
DHD
t
MSB
= t
1
SL
Rev. 0 | Page 13 of 92
UCLK
1
t
DF
/2
CD
Min
2 × t
1 × t
2 × t
0
.
UCLK
UCLK
UCLK
t
BIT 6 TO BIT 1
DR
BIT 6 TO BIT 1
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
t
SR
HCLK
HCLK
LSB IN
t
SF
Max
2 × t
12.5
12.5
12.5
12.5
LSB
ADuC7128/ADuC7129
t
SFS
HCLK
+ 2 × t
UCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns