ADUC7128BCPZ126-RL Analog Devices Inc, ADUC7128BCPZ126-RL Datasheet - Page 54

• Manufacturer Part Number: ADUC7128BCPZ126-RL
• Description: IC,MICROCONTROLLER,16-BIT,ARM7 CPU,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Size: 126KB (126K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7128BCPZ126-RLTR

ADuC7128/ADuC7129
Table 68. QENCON MMR Bit Designations
Bit
15:11
10
9
8
7
6
5
4
3
2
1
0
Table 69. QENSTA MMR Bit Designations
Bit
7:5
4
3
2
1
0
QENDAT Register
Name
QENDAT
The QENDAT register holds the maximum value allowed for the
QENVAL register. If the QENVAL register increments past the
value in this register, an overflow condition occurs. When an over-
flow occurs, the QENVAL register is reset to 0x0000. When the
QENVAL register decrements past zero during an underflow,
it is loaded with the value in QENDAT.
Name
RSVD
FILTEN
RSVD
S2INV
S1INV
DIRCON
S1IRQEN
RSVD
UIRQEN
OIREQEN
RSVD
ENQEN
Name
RSVD
S1EDGE
RSVD
UNDER
OVER
DIR
Address
0xFFFF0F08
Description
Reserved.
Set to 1 by the user to enable filtering on the S1 pin.
Cleared by user to disable filtering on the S1 pin.
Reserved. This bit should be set to 0 by the user.
Set to 1 by the user to invert the S2 input.
Cleared by user to use the S2 input as normal.
If the DIRCON bit is set, then S2INV controls the direction of the counter.
Set to 1 by the user to invert the S1 input.
Cleared by user to use the S1 input as normal.
Direction Control.
Set to 1 by the user to generate an IRQ when a low-to-high transition is detected on S1.
Cleared by the user to disable the interrupt.
This bit should be set to 0 by the user.
Underflow IRQ Enable.
Overflow IRQ Enable.
This bit should be set to 0 by the user.
Quadrature Encoder Enable.
Description
Reserved.
S1 Rising Edge.
Reserved.
Underflow Flag.
This bit is set automatically if an overflow has occurred.
Cleared by reading QENSTA.
Direction of the Counter.
Set to 1 by the user to enable the quadrature encoder.
Cleared by user to disable the quadrature encoder.
Set to 1 by the user to generate an interrupt if QENVAL underflows.
Cleared by the user to disable the interrupt.
Set to 1 by the user to generate an interrupt if QENVAL overflows.
Cleared by user to disable the interrupt.
This bit is set automatically on a rising edge of S1.
Cleared by reading QENSTA.
This bit is set automatically if an underflow occurs.
Cleared by reading QENSTA.
Set to 1 by hardware to indicate that the counter is incrementing.
Set to 0 by hardware to indicate that the counter is decrementing.
In this case, set to 1 by the user to operate the counter in increment mode.
Cleared by user to operate the counter in decrement mode.
Set to 1 by the user to enable S1 as the input to the counter clock. The direction of the counter is controlled
via the S2INV bit.
Cleared by user to operate in normal mode.
Default Value
0Xffff
Access
R/W
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QENVAL Register
Name
QENVAL
The QENVAL register contains the current value of the quadrature
encoder counter.
Address
0xFFFF0F0C
Default Value
0x0000
Access
R/W