CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 37

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

DS679A2
4.5
4.5.1
Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked
into or out of the device.
The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control
pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in
Slave Mode. The value on the SDOUT pin is latched immediately after powering up in hardware mode.
Hardware
Software
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based
on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will
then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-
alone control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Control:
Control:
*MCLKDIV2 must be enabled.
Auto-Detect
Mode only)
(Software
Disabled
Enabled
“MIC Power Control & Speed Control (Address 03h)” on page
page
“SDOUT, M/S” pin
29
“MCLKDIV2” pin 2
1024, 1536, 2048*,
1536, 2048, 3072
55.
512, 768, 1024,
Pin
3072*
QSM
47 kΩ Pull-down Slave
47 kΩ Pull-up
LO
HI
Setting
256, 384, 512, 768,
Table 3. MCLK/LRCK Ratios
512, 768, 1024*,
1024, 1536
1536*
HSM
Master
No Divide
MCLK is divided by 2 prior to all internal circuitry.
256, 384, 512*, 768* 128, 192, 256*, 384*
128, 192, 256, 384,
512, 768
48,
SSM
Selection
“DAC Control (Address 09h)” on
128, 192, 256, 384
DSM
CS42L51
37