CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 71

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

DS679A2
6.27
6.28
CHRG_FREQ
Reserved
7
7
3
Status (Address 20h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: x
Function:
Indicates an invalid MCLK to LRCK ratio. See
Note:
Signal Processing Engine Overflow (MIXX_OVFL)
Default: x
Function:
Indicates a digital overflow condition within the data path after the signal processing engine.
PCMX Overflow (PCMX_OVFL)
Default: x
Function:
Indicates a digital overflow condition within the data path of the PCM mix.
ADC Overflow (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42L51 ADC signal path of each of the
associated ADC’s.
Charge Pump Frequency (Address 21h)
Charge Pump Frequency (CHRG_FREQ[3:0])
Default: 0101
Function:
Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs,
should the switching frequency interfere with other system frequencies such as those in the AM radio band.
Note:
15
...
N
0
CHRG_FREQ
SP_CLKERR
On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
CHRG_FREQ[3:0]
Distortion performance may be affected.
6
6
2
0000
1111
...
CHRG_FREQ
SPEA_OVFL
5
5
1
Frequency
64xFs
---------------- -
N
CHRG_FREQ
SPEB_OVFL
+
2
4
4
0
“Serial Port Clocking” on page 37
PCMA_OVFL PCMB_OVFL ADCA_OVFL
Reserved
3
3
Reserved
2
2
for valid clock ratios.
Reserved
1
1
CS42L51
ADCB_OVFL
Reserved
0
0
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