CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 43

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

DS679A2
SCL
SDA
START
the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit. The ACK bit is output from the
the microcontroller after each transmitted byte.
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As
shown in
stop condition. The following pseudocode illustrates an aborted write operation followed by a read oper-
ation.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
SDA
SCL
0
1
CHIP ADDRESS (WRITE)
1
0
Send start condition.
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
START
0
2
Figure
1
3
0
1
0 1 AD0 0
CHIP ADDRESS (WRITE)
4
1
0
5
0
26, the write operation is aborted after the acknowledge for the MAP byte by sending a
2
6
1
3
7
0
ACK
4
8
1
5
9
INCR
AD0
6
10 11
Figure 26. Control Port Timing, I²C Read
Figure 25. Control Port Timing, I²C Write
6
7
0
5
MAP BYTE
ACK
12 13 14 15
8
4
INCR
CS42L51
9
3
10 11
6
2
MAP BYTE
5
1
12
16
0
4
after each input byte is read, and is input to the
ACK
13 14 15
STOP
3
17 18
START
2
1
19
1
16 17 18
0
ACK
20 21 22 23 24
CHIP ADDRESS (READ)
0
0
7
1
19
6
DATA
0
1 AD0 1
24 25
1
25
0
ACK
26 27 28
26
ACK
27 28
7
DATA +1
7
6
DATA
0
1
ACK
0
DATA +1
7
7
DATA +n
0
6
1
DATA + n
7
0
CS42L51
CS42L51
ACK
0
STOP
ACK
NO
STOP
from
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