CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 11

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

DS692PP1
1.2
RXP/RXN[1:0]
VA
AGND
SAOF
MS_SEL
NV/RERR
V/AUDIO
XTI
XTO
Pin Name
Hardware Mode
Pin #
10
11
12
1
2
5
6
3
4
7
8
9
AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3 or S/PDIF encoded digital
data. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer; and RXN[1:0]
comprise the inverting inputs of the input multiplexer. Unused inputs should be tied to AGND.
Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that
this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of
the recovered clock.
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
Serial Audio Output Format Select (Input) - Used to select the serial audio output format after
reset. See
Master/Slave Select (Input) - Used to select Master or Slave settings for the input and output serial
audio ports after reset. See
Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is output by
default, RERR is selected by a 20 kΩ resistor to VL.
Validity Data/AUDIO (Output) - If a 20 kΩ pull-down is present on this pin, it will output serial Validity
data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. If a
20 kΩ pull-up is present, the pin will be low when valid linear PCM data is present at the AES3 input.
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See
on page
Crystal Out (Output) - Crystal output for Master clock. See
MS_SEL
AGND
SAOF
RXN0
RXN1
RXP0
RXP1
38.
VA
Table 4 on page 41
1
2
3
4
5
6
7
8
32
9
10
31
Table 5 on page 41
for format settings.
11
30
32-Pin QFN Package
Thermal Pad
Top-Down View
29
12
13
28
Pin Description
14
27
for format settings.
15
26
25
16
“SRC Master Clock” on page
18
24
23
22
21
20
19
17
OSCLK2
SDOUT2
VL
DGND
VD_FILT
V_REG
TX/U
C
“SRC Master Clock”
CS8422
38.
11