CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 40

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

40
8.1
MCLK_OUT
Pin Name
NV/RERR
SDOUT1
V/AUDIO
MS_SEL
RX_SEL
TX_SEL
RMCK
SAOF
TX/U
Hardware Mode Serial Audio Port Control
The CS8422 uses the resistors attached to the MS_SEL and SAOF pins to determine the modes of opera-
tion for its serial output ports. After a RST is asserted, the resistor value and condition (VL or GND) are
sensed. This operation will take approximately 4 ms to complete. The SRC_UNLOCK pin will remain high
and both SDOUT pins will be muted until the mode detection sequence has completed. After this, if all clocks
are stable, SRC_UNLOCK will be brought low when audio output is valid and normal operation will begin.
The resistor attached to each mode selection pin should be placed physically close to the CS8422. The end
of the resistor not connected to the mode selection pins should be connected as close as possible to VL and
GND to minimize noise.
Table 4
urations. In the case of SDOUT2, the output resolution depends on the resolution of the incoming AES3-
compatible data. In Right-Justified Modes, the serial format word-length will be equal to the AES3 input data
resolution. The exception is the case where Right-Justified Mode is selected and the AES3 input word-
length is an odd number of bits. In this case, the SDOUT2 word-length will be zero-stuffed to be 1 bit longer
then the AES3 input word-length (example: a 19-bit AES3 input word will result in an 20-bit right-justified
serial format). For a more detailed description of serial formats, refer to
Table 5
MS_SEL pin configurations. For SDOUT1, when the serial port is set to master mode, the master clock ratio
C
shows the Hardware Mode options for output serial port format and the required SAOF pin config-
shows the Hardware Mode master/slave and clock options for both serial ports, and the required
Enables or Disables De-emphasis
Selects TX pass-through output or
Selects RX Input to be output on
Selects data format for SDOUT1
Selects master clock source for
Selects master clock source for
Selects master/slave and clock
Selects either incoming Validity
data output or AUDIO indicator
Selects Active AES3 RX Input
Selects Software or Hardware
Selects error signal output on
configuration for SDOUT1&
incoming U data output
SDOUT1 serial port
Description
Auto-detect
& SDOUT2
NV/RERR
SDOUT 2
the SRC
TX pin
output
Mode
Table 4
Table 3. Hardware Mode Control Settings
and
Table 5
show the pin functions and their corresponding settings.
20 kΩ pull-up on RERR/NVERR
20 kΩ pull-up on MCLK_OUT
20 kΩ pull-down on V/AUDIO
No pull-up on RERR/NVERR
20 kΩ pull-up on V/AUDIO
20 kΩ pull-up on SDOUT1
No pull-up on MCLK_OUT
20 kΩ pull-up on RMCK
No pull-up on SDOUT1
Pin Configuration
No pull-up on RMCK
Connected to GND
Connected to GND
20 kΩ pull-up on U
20 kΩ pull-up on C
Connected to VL
Connected to VL
No pull-up on U
No pull-up on C
See
See
Table 4 on page 41
Table 5 on page 41
Section 5. on page
De-emphasis Auto-detect
De-emphasis Auto-detect
AUDIO indicator output
RXP0/RXN0 is active
RXP1/RXN1 is active
Validity data output
RXP0/RXN0 to TX
RXP1/RXN1 to TX
TX Pass-through
Hardware Mode
Software Mode
Ring Oscillator
U Data Output
Selection
PLL Clock
Disabled
Enabled
XTI-XTO
NVERR
RMCK
RERR
24.
CS8422
DS692PP1