CY7C1355C-133BGCT Cypress Semiconductor Corp, CY7C1355C-133BGCT Datasheet - Page 11

• Manufacturer Part Number: CY7C1355C-133BGCT
• Description: CY7C1355C-133BGCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1355C-133BGCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

tri-state the output drivers. As a safety precaution, DQs and
DQP
write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct BW
inputs must be driven in each cycle of the burst write, in order to
write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Document Number: 38-05539 Rev. *H
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
X
are automatically tri-stated during the data portion of a
3
, must remain inactive for the duration of t
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
1
, CE
Single Write Accesses
2
, and CE
Description
3
) and WE inputs are
ZZREC
after the
section
1
, CE
2
X
,
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
Test Conditions
DD
DD
Address
Address
A1: A0
A1: A0
– 0.2 V
– 0.2 V
First
First
00
01
10
00
01
10
11
11
Address
Address
Second
Second
A1: A0
A1: A0
CY7C1355C, CY7C1357C
01
00
11
10
01
10
11
00
2t
Min
CYC
–
–
–
0
DD
Address
Address
A1: A0
A1: A0
)
Third
Third
10
00
01
10
00
01
11
11
2t
2t
Max
50
CYC
CYC
–
–
Address
Address
Page 11 of 32
Fourth
A1: A0
Fourth
A1: A0
Unit
mA
ns
ns
ns
ns
11
10
01
00
11
00
01
10
[+] Feedback