DSPIC33FJ32GP204-H/PT Microchip Technology, DSPIC33FJ32GP204-H/PT Datasheet
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DSPIC33FJ32GP204-H/PT Summary of contents
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... Microchip Technology Inc. dsPIC33FJ16GP304 High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70290G ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Four processor exceptions On-Chip Flash and SRAM: • Flash program memory ( Kbytes) • Data SRAM (2 Kbytes) • Boot and General Security for Program Flash © 2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • ...
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... Low-power, high-speed Flash technology • Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low-power consumption Packaging: • 28-pin SPDIP/SOIC/SSOP/QFN-S • 44-pin QFN/TQFP Note: See Table 1 for the exact peripheral features per device. © 2011 Microchip Technology Inc. ...
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... The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CONTROLLER FAMILIES Device dsPIC33FJ32GP202 28 32 dsPIC33FJ32GP204 44 32 dsPIC33FJ16GP304 44 16 Note 1: Only two out of three timers are remappable. 2: Only two out of three interrupts are remappable. ...
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... AN12/RP12 2 20 PGEC2/TMS/RP11 3 19 dsPIC33FJ32GP202 PGED2/TDI/RP10/CN16/RB10 CAP Vss TDO/SDA1/RP9 Table 1 = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN24/RB6 = Pins are tolerant (1) /CN13/RB13 (1) /CN14/RB12 (1)(1) /CN15/RB11 (1) /CN21/RB9 for the list of available peripherals. © 2011 Microchip Technology Inc. ...
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... Note 1: The RPn pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to Vss externally. © 2011 Microchip Technology Inc. 11 AN11/RP13 23 AN12/RP12 24 10 PGEC2/RP11 PGED2/RP10 dsPIC33FJ32GP204 dsPIC33FJ16GP304 RP25 30 4 RP24 31 3 RP23 RP22 32 2 ...
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... OSC2/CLKO/CN29/RA3 TDO/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See DS70290G-page 8 11 AN11/RP13 AN12/RP12 25 9 PGEC2/RP11 26 8 PGED2/RP10 CAP dsPIC33FJ32GP204 dsPIC33FJ16GP304 5 29 RP25 4 30 RP24 3 31 RP23 2 32 RP22/CN18/RC6 1 SDA1 33 Table 1 for the list of available peripherals. = Pins are tolerant ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2011 Microchip Technology Inc. to receive the most current information on all of our products. DS70290G-page 9 ...
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... NOTES: DS70290G-page 10 © 2011 Microchip Technology Inc. ...
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... Figure 1-1 shows a general block diagram of the core and peripheral modules dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. Reference in in the DS70290G-page 11 ...
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... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ UART1 ADC1 PWM1-2 CNx I2C1 SPI1 PORTA PORTB 16 PORTC Remappable Pins “Pin Diagrams” for the specific pins © 2011 Microchip Technology Inc. ...
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... No Legend: CMOS = CMOS compatible input or output Schmitt Trigger input with CMOS levels; PPS = Peripheral Pin Select © 2011 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for analog modules. This pin must be connected at all times. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input Output Power I = Input © 2011 Microchip Technology Inc. ...
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... ADC module is implemented Note: The AV and AV pins must connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Overstress (EOS). Ensure that the MCLR pin Section 22 additional Section 19.2 and V ) and fast signal shown in Figure 2- Figure 2-2 within EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL © 2011 Microchip Technology Inc. ...
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... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “ ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor between V and the unused pins. DS70290G-page 18 SS © 2011 Microchip Technology Inc. ...
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... A block diagram of the CPU is shown in programmer’s model for the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 is shown in Figure © 2011 Microchip Technology Inc. 3.1 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory ...
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... X Data Bus Data Latch Data Latch PCL X RAM Y RAM Address Loop Address Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU 16 To Peripheral Modules © 2011 Microchip Technology Inc. ...
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... Registers AD39 DSP AccA Accumulators AccB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 ...
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... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70290G-page 22 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2011 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2011 Microchip Technology Inc. (2) DS70290G-page 23 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70290G-page 24 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
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... W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2011 Microchip Technology Inc. 3.6 DSP Engine and The ...
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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70290G-page 26 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. © 2011 Microchip Technology Inc. 3.6.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • ...
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... MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. to data saturation (see Saturation”). For © 2011 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2011 Microchip Technology Inc. 3.6.3 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70290G-page 30 © 2011 Microchip Technology Inc. ...
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... Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) © 2011 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33FJ32GP202/204 and devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector least significant word Instruction Width Table”. PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so and care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70290G-page 34 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near data space © 2011 Microchip Technology Inc. ...
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... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class). © 2011 Microchip Technology Inc. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 ...
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TABLE 4-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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TABLE 4-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
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... TABLE 4-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
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... TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC ...
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TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-19: PORTC REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02D0 — — ...
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TABLE 4-20: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2011 Microchip Technology Inc. 4.2.7 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM and protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...
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... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2011 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. Note: Y space calculations assume word sized data (LSB of every EA is always clear). The length of a circular buffer is not directly specified ...
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... If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV<15>), a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. © 2011 Microchip Technology Inc. N bytes, be enabled will ...
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... TABLE 4-24: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2011 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal ...
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... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx © 2011 Microchip Technology Inc. show how the program EA is <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...
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... Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2011 Microchip Technology Inc. Program Counter 0 23 bits ...
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... TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area. Section 5.0 “Flash © 2011 Microchip Technology Inc. ...
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... PSVPAG is mapped into the upper half of the data memory space... © 2011 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... NOTES: DS70290G-page 56 © 2011 Microchip Technology Inc. ...
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... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. ground (V SS customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be pro- grammed ...
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... TIME 11064 Cycles = × × 0.05 1 0.00375 – Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 – 1 0.00375 – (Register 5-1) controls which 5- write-only register that is the user application must to Section 5.3 “Programming © 2011 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> bits are unimplemented. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 ...
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... NVMKEY<7:0>: Key Register (Write Only) bits DS70290G-page 60 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2011 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2011 Microchip Technology Inc. ...
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... V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected ...
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... SWDTEN bit setting. DS70290G-page 64 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2011 Microchip Technology Inc. (1) (CONTINUED) DS70290G-page 65 ...
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... T T OST LOCK T T OST LOCK — T LOCK T — OST — — Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2011 Microchip Technology Inc. ...
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... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2011 Microchip Technology Inc. Vbor V BOR ...
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... The reset delay (T BOR rises above the V Value is too low DD crosses DD has elapsed. The BOR ) is programmed by PWRT Reset Timer Value Select bits Section 19.0 “Special Features” initiated each time V PWRT DD trip point BOR © 2011 Microchip Technology Inc. ...
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... Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. © 2011 Microchip Technology Inc BOR PWRT ...
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... W register access or Security Reset Configuration Mismatch MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR for more information on Cleared by: POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR — — © 2011 Microchip Technology Inc. ...
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... These are summarized in Table 7-1 and Table 7-2. © 2011 Microchip Technology Inc. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in AIVT ...
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... Table 7-1 for the list of implemented interrupt vectors. DS70290G-page 72 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... Reserved AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2011 Microchip Technology Inc. ...
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... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2011 Microchip Technology Inc. 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
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... R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Register 3-2. R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
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... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
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... STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70290G-page 78 © 2011 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request has not occurred DS70290G-page 80 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70290G-page 81 ...
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... Interrupt request has not occurred DS70290G-page 82 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... Interrupt request not enabled DS70290G-page 84 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... REGISTER 7-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. DS70290G-page 85 ...
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... Interrupt request not enabled DS70290G-page 86 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
Page 88
... Interrupt is priority 1 000 = Interrupt source is disabled DS70290G-page 88 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 89
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
Page 90
... Interrupt is priority 1 000 = Interrupt source is disabled DS70290G-page 90 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
Page 92
... Interrupt is priority 1 000 = Interrupt source is disabled DS70290G-page 92 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
Page 94
... Unimplemented: Read as ‘0’ DS70290G-page 94 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 95
... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 96
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70290G-page 96 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 97
... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2011 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 98
... NOTES: DS70290G-page 98 © 2011 Microchip Technology Inc. ...
Page 99
... Throughout this document F be different when Doze mode is used in any ratio other than 1:1, which is the default © 2011 Microchip Technology Inc. The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 oscillator system provides: • External and internal oscillator options as clock sources. ...
Page 100
... PLL output frequency ( the range of 12.5 MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. © 2011 Microchip Technology Inc. for further details.) Configuration bits, Table 8-1. ...
Page 101
... Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2011 Microchip Technology Inc. ’, • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a IN VCO output 160 MHz, which is within the 100-200 MHz ranged needed. • ...
Page 102
... This register is reset only on a Power-on Reset (POR). DS70290G-page 102 (1,3) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) © 2011 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Clear only bit x = Bit is unknown ...
Page 103
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1,3) (CONTINUED) DS70290G-page 103 ...
Page 104
... This register is reset only on a Power-on Reset (POR). DS70290G-page 104 (2) R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 105
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input/33 • • • 00001 = Input/3 00000 = Input/2 (default) Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) (CONTINUED) DS70290G-page 105 ...
Page 106
... This register is reset only on a Power-on Reset (POR). DS70290G-page 106 (1) U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 107
... The OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) U-0 U-0 U-0 — ...
Page 108
... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. Section 7. “Oscillator” © 2011 Microchip Technology Inc. ...
Page 109
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 110
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). There are eight possible ® DSC © 2011 Microchip Technology Inc. ...
Page 111
... AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins multiplexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — ...
Page 112
... Output Compare 1 module is enabled DS70290G-page 112 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown ...
Page 113
... WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. ...
Page 114
... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Example 10-1 dsPIC33FJ32GP202/204 and © 2011 Microchip Technology Inc. ...
Page 115
... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. 10.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 116
... U1TX Output U1RTS Output OC1 Output OC2 Output Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPnR<4:0> Output Enable RPn Output Data 18 19 © 2011 Microchip Technology Inc. ...
Page 117
... OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) ® See MPLAB IDE Help for more information. © 2011 Microchip Technology Inc. RPn tied to default port pin 00000 RPn tied to UART1 Transmit 00011 RPn tied to UART1 Ready To Send 00100 RPn tied to SPI1 Data Output ...
Page 118
... Unimplemented: Read as ‘0’ DS70290G-page 118 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 119
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R< ...
Page 120
... Input tied to RP1 00000 = Input tied to RP0 DS70290G-page 120 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 121
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> ...
Page 122
... Input tied to RP1 00000 = Input tied to RP0 DS70290G-page 122 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 123
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR< ...
Page 124
... Input tied to RP1 00000 = Input tied to RP0 DS70290G-page 124 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 125
... SDI1R<4:0>: Assign SPI 1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R< ...
Page 126
... Input tied to RP1 00000 = Input tied to RP0 DS70290G-page 126 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 127
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin (see function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin (see function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...
Page 128
... Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for peripheral Table 10-2 for peripheral R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for peripheral Table 10-2 for peripheral © 2011 Microchip Technology Inc. ...
Page 129
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin (see eral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...
Page 130
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 131
... RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R< ...
Page 132
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 133
... RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R< ...
Page 134
... NOTES: DS70290G-page 134 © 2011 Microchip Technology Inc. ...
Page 135
... SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2011 Microchip Technology Inc. Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal ...
Page 136
... Unimplemented: Read as ‘0’ DS70290G-page 136 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 137
... Only T2CON control bit is used for setup and control. Timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2011 Microchip Technology Inc. 12.1 32-Bit Operation To configure the Timer2/3 feature for 32-bit operation: 1. ...
Page 138
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70290G-page 138 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2011 Microchip Technology Inc. ...
Page 139
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2011 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70290G-page 139 ...
Page 140
... Unimplemented: Read as ‘0’ DS70290G-page 140 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 141
... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), these bits have no effect. © 2011 Microchip Technology Inc. U-0 U-0 (1) — ...
Page 142
... NOTES: DS70290G-page 142 © 2011 Microchip Technology Inc. ...
Page 143
... ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2011 Microchip Technology Inc. • Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin • ...
Page 144
... Input capture module turned off DS70290G-page 144 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE HC = Cleared in hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 145
... TMR3 TMR2 © 2011 Microchip Technology Inc. The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value ...
Page 146
... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match — © 2011 Microchip Technology Inc. ...
Page 147
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 148
... NOTES: DS70290G-page 148 © 2011 Microchip Technology Inc. ...
Page 149
... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2011 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The SPI module is compatible with ® ...
Page 150
... Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70290G-page 150 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 151
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DISSCK DISSDO ...
Page 152
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS70290G-page 152 (3) (3) © 2011 Microchip Technology Inc. ...
Page 153
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 154
... NOTES: DS70290G-page 154 © 2011 Microchip Technology Inc. ...
Page 155
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2011 Microchip Technology Inc. 16.1 Operating Modes The hardware fully implements all the master and slave 2 functions of the I C Standard and Fast mode specifications, as well as 7-bit and 10-bit addressing ...
Page 156
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2011 Microchip Technology Inc. ...
Page 157
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2011 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 158
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70290G-page 158 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master master) © 2011 Microchip Technology Inc. ...
Page 159
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2011 Microchip Technology Inc. U-0 U-0 R/C-0 HS — — ...
Page 160
... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70290G-page 160 2 C slave device address byte. © 2011 Microchip Technology Inc. ...
Page 161
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 162
... NOTES: DS70290G-page 162 © 2011 Microchip Technology Inc. ...
Page 163
... Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2011 Microchip Technology Inc. The primary features of the UART module are: • Full-Duplex, 8-bit or 9-bit Data Transmission through the UxTX and UxRX pins • Even, odd or no parity options (for 8-bit data) • ...
Page 164
... DS70290G-page 164 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 165
... Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2011 Microchip Technology Inc. MODE REGISTER (CONTINUED) x DS70290G-page 165 ...
Page 166
... U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR C = Clear only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 167
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2011 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x DS70290G-page 167 ...
Page 168
... NOTES: DS70290G-page 168 © 2011 Microchip Technology Inc. ...
Page 169
... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the specific device data sheet for further details. A block diagram of in dsPIC33FJ16GP304 and dsPIC33FJ32GP204 devices is shown in Figure 18-1. A block diagram of the ADC for the dsPIC33FJ32GP202 Figure 18-2. 18.2 ...
Page 170
... FIGURE 18-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16GP304 AND dsPIC33FJ32GP204 DEVICES AN0 AN12 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V REFL CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 AN9 V REFL CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 ...
Page 171
... AN2 AN5 CH123SA CH123SB (2) CH3 AN11 V REFL CH123NA CH123NB Alternate Input Selection Note inputs can be multiplexed with other analog inputs. REF REF 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. © 2011 Microchip Technology Inc (1) ( REF ...
Page 172
... T 2: See the ADC Electrical Characteristics for the exact RC clock value. DS70290G-page 172 AD1CON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 when the PLL is enabled. If the PLL is not used, F OSC = 1/F . OSC OSC AD1CON3<15> equal OSC © 2011 Microchip Technology Inc. ...
Page 173
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2011 Microchip Technology Inc. U-0 U-0 — — ...
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... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. DS70290G-page 174 © 2011 Microchip Technology Inc. ...
Page 175
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2011 Microchip Technology Inc. U-0 U-0 — — ...
Page 176
... This bit only used if AD1CON1<7:5> (SSRC<2:0>) = 111. 2: This bit is not used if AD1CON3<15> (ADRC DS70290G-page 176 R/W-0 R/W-0 R/W-0 (1) SAMC<4:0> R/W-0 R/W-0 R/W-0 (2) ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ( © 2011 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 177
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 178
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 179
... Channel 0 negative input is AN1 0 = Channel 0 negative input is V bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 ...
Page 180
... REGISTER 18-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED) bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits dsPIC33FJ32GP204 and dsPIC33FJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 181
... PCFGx = ANx, where through 12. 3: The PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx Register. In this case, all port pins multiplexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 CSS12 ...
Page 182
... NOTES: DS70290G-page 182 © 2011 Microchip Technology Inc. ...
Page 183
... Legend: — = unimplemented bit, read as ‘0’. Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’. 2: These bits are reserved and always read as ‘1’. © 2011 Microchip Technology Inc. 19.1 Configuration Bits dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices provide nonvolatile memory implementation and for device configuration bits ...
Page 184
... RTSP Bit Field Register Effect BWRP FBS Immediate Boot Segment Program Flash Write Protection BSS<2:0> FBS Immediate dsPIC33FJ32GP202 and dsPIC33FJ32GP204 Devices Only BSS<2:0> FBS Immediate dsPIC33FJ16GP304 Devices Only GSS<1:0> FGS Immediate General Segment Code-Protect bit GWRP FGS Immediate General Segment Write-Protect bit ...
Page 185
... FICD Immediate JTAG Enable bit ICS<1:0> FICD Immediate ICD Communication Channel Select bits © 2011 Microchip Technology Inc. Description 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled 1 = Allow only one re-configuration ...
Page 186
... The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should V voltage. (1) CAP . The main purpose of the BOR CAP fall below the BOR threshold DD © 2011 Microchip Technology Inc. ...
Page 187
... CLRWDT Instruction SWDTEN FWDTEN LPRC Clock (divide by N1) WINDIS © 2011 Microchip Technology Inc. 19.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during and Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed ...
Page 188
... GS = 5376 IW 002BFEh 000000h VS = 256 IW 0001FEh 000200h BS = 768 IW 0007FEh 000800h 001FFEh 002000h GS = 4608 IW 002BFEh 000000h VS = 256 IW 0001FEh 000200h 0007FEh BS = 3840 IW 000800h 001FFEh 002000h GS = 1536 IW 002BFEh 000000h VS = 256 IW 0001FEh 000200h 0007FEh BS = 5376 IW 000800h 001FFEh 002000h 002BFEh © 2011 Microchip Technology Inc. ...
Page 189
... In-Circuit Serial Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 © 2011 Microchip Technology Inc. 19.8 In-Circuit Debugger ® When MPLAB ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled ...
Page 190
... NOTES: DS70290G-page 190 © 2011 Microchip Technology Inc. ...
Page 191
... The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2011 Microchip Technology Inc. Most bit-oriented rotate/shift instructions) have two operands: • The W register (with or without an address ...
Page 192
... Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Programmer’s (DS70157). Description Reference Manual” © 2011 Microchip Technology Inc. ...
Page 193
... Y data space prefetch address register for DSP instructions ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4...W7} Wyd © 2011 Microchip Technology Inc. Description DS70290G-page 193 ...
Page 194
... Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws © 2011 Microchip Technology Inc Status Flags Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV ...
Page 195
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2011 Microchip Technology Inc Description Words Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...
Page 196
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) Prefetch and store accumulator © 2011 Microchip Technology Inc Status Flags Cycles Affected 1 18 N,Z,C,OV 1 ...
Page 197
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2011 Microchip Technology Inc Description Words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 198
... Wn = nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws © 2011 Microchip Technology Inc Status Flags Cycles Affected N,Z ...
Page 199
... PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2011 Microchip Technology Inc. 21.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 200
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2011 Microchip Technology Inc. ...