DSPIC33FJ32GP204-H/PT Microchip Technology, DSPIC33FJ32GP204-H/PT Datasheet - Page 275

• Manufacturer Part Number: DSPIC33FJ32GP204-H/PT
• Description: 16-bit DSC, 44LD,32KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP204-H/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-TQFP
• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 140 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Revision G (January 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of V
All other major changes are referenced by their
respective section in the following table.
TABLE A-6:
© 2011 Microchip Technology Inc.
High-Performance, 16-bit Digital Signal
Controllers
Section 2.0 “Guidelines for Getting Started
with 16-bit Digital Signal Controllers”
Section 3.0 “CPU”
Section 4.0 “Memory Organization”
Section 8.0 “Oscillator Configuration”
Section 18.0 “10-bit/12-bit Analog-to-Digital
Converter (ADC)”
Section 19.0 “Special Features”
Section 24.0 “Packaging Information”
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DDCORE
Section Name
MAJOR SECTION UPDATES
have been removed.
Added the SSOP package information (see “Packaging:”,
and
Updated the title of
Connection
The frequency limitation for device PLL start-up conditions was
updated in
Start-up”.
The second paragraph in
Removed references to DMA in the CPU Core Block Diagram (see
Figure
Updated the data memory reference in the third paragraph in
Section 4.2 “Data Address
The All Resets values for the following SFRs in the Timer Register
Map were changed (see
• TMR1
• TMR2
• TMR3
Added Note 3 to the OSCCON: Oscillator Control Register (see
Register
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register
Updated the V
(see
Added a new paragraph and removed the third paragraph in
Section 19.1 “Configuration
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see
Added the 28-Lead SSOP package information (see
“Package Marking Information”
Details”).
“Pin
Figure 18-1
3-1).
8-1).
8-2).
8-3).
8-4).
Diagrams”).
Section 2.7 “Oscillator Value Conditions on Device
(Vcap)”.
REFL
and
Table
Section 2.3 “CPU Logic Filter Capacitor
references in the ADC1 module block diagrams
Figure
Update Description
19-2).
Table
Section 2.9 “Unused I/Os”
18-2).
Space”.
Bits”.
4-5):
and
Section 24.2 “Package
DS70290G-page 275
Section 24.1
was updated.
Table
1,