EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 103
EP2SGX90EF1152I4
Manufacturer Part Number
EP2SGX90EF1152I4
Description
Stratix II GX
Manufacturer
Altera
Datasheet
1.EP2SGX90EF1152I4.pdf
(316 pages)
Specifications of EP2SGX90EF1152I4
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Not Compliant
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Figure 2–67. Global Clock Control Blocks
Notes to
(1)
(2)
Figure 2–68. Regional Clock Control Blocks
Notes to
(1)
(2)
Altera Corporation
October 2007
These clock select signals can be dynamically controlled through internal logic when the device is operating in user
mode.
These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object
File [.pof]) and cannot be dynamically controlled during user mode operation.
These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
controlled during user mode operation.
Only the CLKn pins on the top and bottom of the device feed to regional clock select.
Figure
Figure
2–67:
2–68:
CLKSELECT[1..0]
(1)
This multiplexer supports
User-Controllable
Dynamic Switching
Figures 2–67
clock, regional clock, and PLL external clock output, respectively.
PLL Counter
PLL Counter
Outputs
Outputs
2
2
through
2
CLKp
CLKp
Pins
Pin
Enable/
Disable
RCLK
2
CLKn
Pin
2–69
Enable/
Disable
GCLK
CLKn
Pin
(2)
Internal
show the clock control block for the global
Logic
Static Clock Select (1)
Internal
Logic
Internal
Logic
Internal
Static Clock Select
Logic
Stratix II GX Device Handbook, Volume 1
(2)
Stratix II GX Architecture
2–95
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