EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 131

• Manufacturer Part Number: EP2SGX90EF1152I4
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Not Compliant

Figure 2–86. DQS Phase-Shift Circuitry
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
October 2007
to IOE
DQSn
Pin
Δt
There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II GX device. There
are up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
The “t” module represents the DQS logic block.
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the
phaseshift circuitry.
You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
Figure
to IOE
DQS
Pin
Δt
2–86:
to IOE
DQSn
Pin
Δt
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Stratix II GX device has two phase-shifting reference circuits, one on
the top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]p feed the phase circuitry on the top of the device and
clock pins CLK[7..4]p feed the phase circuitry on the bottom of the
device. In addition, PLL clock outputs can also feed the phase-shifting
reference circuits.
control of each DQS delay shift on the top of the device. This same circuit
is duplicated on the bottom of the device.
to IOE
DQS
Pin
Δt
CLK[15..12]p (3)
Notes
Phase-Shift
Circuitry
DQS
(1),
Figure 2–86
(2)
From PLL 5 (4)
to IOE
DQS
Pin
Δt
shows the phase-shift reference circuit
Stratix II GX Device Handbook, Volume 1
DQSn
to IOE
Pin
Δt
Stratix II GX Architecture
to IOE
DQS
Pin
Δt
to IOE
DQSn
Pin
Δt
2–123
DQS Logic
Blocks