EP2SGX90EF1152I4 Altera, EP2SGX90EF1152I4 Datasheet - Page 83
EP2SGX90EF1152I4
Manufacturer Part Number
EP2SGX90EF1152I4
Description
Stratix II GX
Manufacturer
Altera
Datasheet
1.EP2SGX90EF1152I4.pdf
(316 pages)
Specifications of EP2SGX90EF1152I4
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Not Compliant
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Quantity
Price
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745
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Figure 2–52. M4K RAM Block LAB Row Interface
Altera Corporation
October 2007
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
M4K RAM Block Local
Interconnect Region
16
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
You cannot use an initialization file to initialize the contents of a M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
datain
control
signals
clocks
LAB Row Clocks
M4K RAM
address
Block
dataout
byte
enable
36
Stratix II GX Device Handbook, Volume 1
6
Stratix II GX Architecture
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
2–75
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