EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet - Page 43

• Manufacturer Part Number: EVAL-ADF7021-VDB2Z
• Description: 868 - 870MHz - EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of EVAL-ADF7021-VDB2Z

• Frequency: 868MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL INTERFACE
The serial interface allows the user to program the 16 32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a level shifter, 32-bit shift register, and 16 latches.
Signals should be CMOS compatible. The serial interface is
powered by the regulator and, therefore, is inactive when CE is low.
Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of 16 latches on the
rising edge of SLE. The destination latch is determined by the
value of the four control bits (C4 to C1); these bits are the four
LSBs, DB3 to DB0, as shown in Figure 2. Data can also be read
back on the SREAD pin.
READBACK FORMAT
The readback operation is initiated by writing a valid control word
to the readback setup register and enabling the READBACK_
SELECT bit (Register 7, Bit DB8 = 1). The readback can begin
after the control word has been latched with the SLE signal. SLE
must be kept high while the data is being read out. Each active
edge at the SCLK pin successively clocks the readback word out
at the SREAD pin, MSB first (see Figure 57). The data appearing
at the first clock cycle following the latch operation must be
ignored. An extra clock cycle is needed after the 16
bit to return the SREAD pin to tristate. Therefore, 18 total clock
cycles are needed for each readback. After the 18
SLE should be brought low.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed, 16-bit integer
comprising Bit RV16 to Bit RV1 and is scaled according to the
following formula:
In the absence of frequency errors, FREQ RB is equal to the IF
frequency of 100 kHz. Note that, for the AFC readback to yield
a valid result, the downconverted input signal must not fall outside
the bandwidth of the analog IF filter. At low input signal levels, the
variation in the readback value can be improved by averaging.
FREQ RB (Hz) = (AFC READBACK × DEMOD CLK)/2
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
FILTER CAL READBACK
READBACK MODE
SILICON REVISION
RSSI READBACK
AFC READBACK
DB15
RV16
RV16
X
X
0
DB14
RV15
RV15
X
X
0
DB13
RV14
RV14
X
X
0
th
clock cycle,
th
DB12
RV13
RV13
readback
X
X
0
Figure 57. Readback Value Table
DB11
RV12
RV12
X
X
0
Rev. 0 | Page 43 of 60
18
DB10
RV11
RV11
LG2
X
0
RV10
RV10
DB9
LG1
X
0
READBACK VALUE
RSSI Readback
The format of the RSSI readback word is shown in Figure 57. It
comprises the RSSI-level information (Bit RV7 to Bit RV1), the
current filter gain (FG2, FG1), and the current LNA gain (LG2,
LG1) setting. The filter and LNA gain are coded in accordance
with the definitions in the Register 9—AGC Register section. For
signal levels below −100 dBm, averaging the measured RSSI values
improves accuracy. The input power can be calculated from the
RSSI readback value as described in the RSSI/AGC section.
Readback with AFC or Linear Demodulation On
To perform any readback with the AFC on, the AGC must first be
locked. To lock the AGC, use the LOCK_THRESHOLD_MODE
bits (Bits[DB5:DB4] in Register 12) for packet reception. The lock
threshold mode locks the threshold of the envelope detector, as
well as the AFC and AGC circuits. It can be set to lock on recep-
tion of a valid SWD and remain locked until it is released by a
subsequent SPI command (LOCK_THRESHOLD_MODE = 1).
It can also be set to lock on reception of a valid SWD for a specified
number of bytes by setting LOCK_THRESHOLD_MODE = 2;
or it can be locked at any time by setting LOCK_THRESHOLD_
MODE = 3. After the threshold is locked, a readback can be
performed. The AGC/AFC lock is released by setting
LOCK_THRESHOLD_MODE = 0.
Battery Voltage/ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV7 to Bit RV1. This also
applies to the readback of the voltage at the ADCIN pin and the
temperature sensor. From the readback information, the battery
or ADCIN voltage can be determined as follows:
The temperature can be calculated as follows:
Temperature (°C) = −40 + [(68.4 − TEMP READBACK) × 9.32]
DB8
RV9
FG2
RV9
X
0
V
V
BATTERY
ADCIN
DB7
RV8
FG1
RV8
RV8
X
= (ADCIN VOLTAGE READBACK)/42.1
DB6
RV7
RV7
RV7
RV7
RV7
= (BATTERY VOLTAGE READBACK)/21.1
DB5
RV6
RV6
RV6
RV6
RV6
DB4
RV5
RV5
RV5
RV5
RV5
DB3
RV4
RV4
RV4
RV4
RV4
DB2
RV3
RV3
RV3
RV3
RV3
DB1
RV2
RV2
RV2
RV2
RV2
ADF7021-V
DB0
RV1
RV1
RV1
RV1
RV1