KSZ8841-16MVLI Micrel Inc, KSZ8841-16MVLI Datasheet - Page 6

• Manufacturer Part Number: KSZ8841-16MVLI
• Description: Single Ethernet Port + Generic (8, 16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MVLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1632 - BOARD EVALUATION KSZ8841-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-2114; KSZ8841-16MVLI

MIB (Management Information Base) Counters............................................................................................................... 85
Absolute Maximum Ratings
Operating Ratings
Electrical Characteristics
Timing Specifications ......................................................................................................................................................... 89
October 2007
Micrel, Inc.
Bank 16 RXQ Memory Information Register (0x0A): RXMIR....................................................................................... 65
Bank 17 TXQ Command Register (0x00): TXQCR ...................................................................................................... 65
Bank 17 RXQ Command Register (0x02): RXQCR ..................................................................................................... 65
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR ........................................................................................ 66
Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR ....................................................................................... 66
Bank 17 QMU Data Register Low (0x08): QDRL ......................................................................................................... 67
Bank 17 QMU Data Register High (0x0A): QDRH ....................................................................................................... 67
Bank 18 Interrupt Enable Register (0x00): IER ............................................................................................................ 68
Bank 18 Interrupt Status Register (0x02): ISR ............................................................................................................. 69
Bank 18 Receive Status Register (0x04): RXSR ......................................................................................................... 70
Bank 18 Receive Byte Count Register (0x06): RXBC.................................................................................................. 70
Bank 18 Early Transmit Register (0x08): ETXR........................................................................................................... 71
Bank 18 Early Receive Register (0x0A): ERXR ........................................................................................................... 71
Bank 19 Multicast Table Register 0 (0x00): MTR0....................................................................................................... 71
Bank 19 Multicast Table Register 1 (0x02): MTR1....................................................................................................... 72
Bank 19 Multicast Table Register 2 (0x04): MTR2....................................................................................................... 72
Bank 19 Multicast Table Register 3 (0x06): MTR3....................................................................................................... 72
Bank 19 Power Management Control and Status Register (0x08): PMCS .................................................................. 72
Banks 20 – 31: Reserved ............................................................................................................................................. 73
Bank 32 Chip ID and Enable Register (0x00): CIDER ................................................................................................. 73
Bank 32 Chip Global Control Register (0x0A): CGCR ................................................................................................. 74
Banks 33 – 41: Reserved ............................................................................................................................................. 74
Bank 42 Indirect Access Control Register (0x00): IACR .............................................................................................. 75
Bank 42 Indirect Access Data Register 1 (0x02): IADR1 ............................................................................................. 75
Bank 42 Indirect Access Data Register 2 (0x04): IADR2 ............................................................................................. 75
Bank 42 Indirect Access Data Register 3 (0x06): IADR3 ............................................................................................. 75
Bank 42 Indirect Access Data Register 4 (0x08): IADR4 ............................................................................................. 75
Bank 42 Indirect Access Data Register 5 (0x0A): IADR5 ............................................................................................ 75
Bank 43– 44: Reserved ................................................................................................................................................ 75
Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR ....................................................................... 76
Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR......................................................................... 77
Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR............................................................................................... 77
Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR ............................................................................................. 78
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR............................................................... 78
Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR ..................................................... 78
Bank 46: Reserved ....................................................................................................................................................... 79
Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT ................................................................................................ 79
Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL ........................................................................ 80
Bank 48: Reserved ....................................................................................................................................................... 80
Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD ................................................................. 81
Bank 49 Port 1 Control Register 4 (0x02): P1CR4....................................................................................................... 82
Bank 49 Port 1 Status Register (0x04): P1SR ............................................................................................................. 83
Banks 50 – 63: Reserved ............................................................................................................................................. 84
Additional MIB Information ........................................................................................................................................... 86
Asynchronous Timing without using Address Strobe (ADSN = 0) ............................................................................... 89
Asynchronous Timing using Address Strobe (ADSN) .................................................................................................. 90
Asynchronous Timing using DATACSN ....................................................................................................................... 91
(1)
............................................................................................................................................................ 87
(1)
................................................................................................................................................ 88
(1)
............................................................................................................................................ 87
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KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6