KSZ8841-16MVLI Micrel Inc, KSZ8841-16MVLI Datasheet - Page 90

• Manufacturer Part Number: KSZ8841-16MVLI
• Description: Single Ethernet Port + Generic (8, 16-bit) Bus Interface( )
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MVLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1632 - BOARD EVALUATION KSZ8841-16MVL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-2114; KSZ8841-16MVLI

Asynchronous Timing using Address Strobe (ADSN)
October 2007
Micrel, Inc.
Notes:
1.
2.
When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read or Write
operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high.
In order to speed up the ARDY low time to 40ns, user has to use the turbo software driver which is only supported in the A6 device.
Please refer to the “KSZ88xx Programmer's Guide” for detail.
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Addr, AEN, BExN
(Read Cycle)
( Write Cycle)
RDN, WRN
Write Data
Read Data
Parameter
A1-A15, AEN, BExN[3:0] valid to RDN, WRN active
Read data valid to ARDY rising
Read data hold to RDN inactive
Write data setup to WRN inactive
Write data hold after WRN inactive
A1-A15, AEN, nBE[3:0] setup to ADSN rising
Read active to ARDY Low
A1-A15, AEN, BExN[3:0] hold after ADSN rising
Write inactive to ARDY Low
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 40ns to
read QMU data register in turbo mode) (Note2)
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 80ns to
read QMU data register in normal mode)
ARDY low (wait time) in write cycle (Note1)
(It is 0ns to write bank select register)
(It is 36ns to write QMU data register)
ADSN
ARDY
ARDY
Table 17. Asynchronous Cycle using ADSN Timing Parameters
Figure 14. Asynchronous Cycle – Using ADSN
t1
t6
valid
t7
90
t10
t8
t4
valid
t2
valid
Min
0
4
4
2
4
2
0
0
0
t3
t5
Typ
t9
40
80
50
KSZ8841-16/32 MQL/MVL/MBL
t11
Max
0.8
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M9999-102207-1.6