KSZ8993M-EVAL Micrel Inc, KSZ8993M-EVAL Datasheet - Page 33

• Manufacturer Part Number: KSZ8993M-EVAL
• Description: KSZ8993M Evaluation Board - For Experimental Use Only
• Manufacturer: Micrel Inc

Specifications of KSZ8993M-EVAL

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The MIIM interface consists of the following:
The following table depicts the MII Management Interface frame format.
For the KSZ8993M, MIIM register access is selected when bit 2 of the PHY address is set to ‘0’. PHY address bits
[4:3] are not defined for MIIM register access, and hence can be set to either 0’s or 1’s in read/write operation.
Serial Management Interface (SMI)
The SMI is the KSZ8993M non-standard MIIM interface that provides access to all KSZ8993M configuration
registers. This interface allows an external device to completely monitor and control the states of the KSZ8993M.
The SMI interface consists of the following:
The following table depicts the SMI frame format.
For the KSZ8993M, SMI register access is selected when bit 2 of the PHY address is set to ‘1’. PHY address bits
[1:0] are not defined for SMI register access, and hence can be set to either 0’s or 1’s in read/write operation.
To access the KSZ8993M registers 0-127 (0x00 – 0x7F), the following applies:
Micrel, Inc.
October 2008
Write
Read
Write
Read
PHYAD[4:3] and REGAD[4:0] are concatenated to form the 7-bits address; that is, {PHYAD[4:3],
REGAD[4:0]} = bits [6:0] of the 7-bits address.
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
Access to a set of six 16-bits registers, consisting of standard MIIM registers [0:5].
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8993M device.
Access to all KSZ8993M configuration registers. Registers access includes the Global, Port and
Advanced Control Registers 0-127 (0x00 – 0x7F), and indirect access to the standard MIIM registers
[0:5].
controller to communicate with the KSZ8993M device.
Preamble
Preamble
32 1’s
32 1’s
32 1’s
32 1’s
Start of
Frame
Start of
Frame
01
01
Table 6. Serial Management Interface (SMI) Frame Format
01
01
Table 5. MII Management Interface Frame Format
Read/Write
OP Code
Read/Write
OP Code
10
01
10
01
PHY
Address
Bits [4:0]
PHY
Address
Bits [4:0]
RR1xx
RR1xx
xx0AA
xx0AA
33
REG
Address
Bits [4:0]
REG
Address
Bits [4:0]
RRRRR
RRRRR
RRRRR
RRRRR
TA
TA
Z0
10
Z0
10
Data
Bits [15:0]
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Data
Bits [15:0]
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
M9999-020606
KSZ8993M/ML
Idle
Idle
Z
Z
Z
Z