KSZ8993M-EVAL Micrel Inc, KSZ8993M-EVAL Datasheet - Page 9

• Manufacturer Part Number: KSZ8993M-EVAL
• Description: KSZ8993M Evaluation Board - For Experimental Use Only
• Manufacturer: Micrel Inc

Specifications of KSZ8993M-EVAL

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Package Information.............................................................................................................................86
List of Figures
Figure 1. Typical Straight Cable Connection .......................................................................................................................................25
Figure 2. Typical Crossover Cable Connection ...................................................................................................................................25
Figure 3. Auto Negotiation and Parallel Operation .............................................................................................................................26
Figure 4. Destination Address Lookup Flow Chart, Stage 1 ..............................................................................................................27
Figure 5. Destination Address Resolution Flow Chart, Stage 2 ........................................................................................................28
Figure 6. 802.1p Priority Field Format ..................................................................................................................................................37
Figure 7. KSZ8993M EEPROM Configuration Timing Diagram..........................................................................................................38
Figure 8. SPI Write Data Cycle...............................................................................................................................................................42
Figure 9. SPI Read Data Cycle ...............................................................................................................................................................42
Figure 10. SPI Multiple Write..................................................................................................................................................................42
Figure 11. SPI Multiple Read..................................................................................................................................................................43
Figure 12. Loopback Path ......................................................................................................................................................................44
Figure 13. EEPROM Interface Input Timing Diagram ..........................................................................................................................76
Figure 14. EEPROM Interface Output Timing Diagram .......................................................................................................................76
Figure 15. SNI Input Timing Diagram....................................................................................................................................................77
Figure 16. SNI Output Timing Diagram.................................................................................................................................................77
Figure 17. MAC-Mode MII Timing – Data Received from MII ..............................................................................................................79
Figure 18. MAC-Mode MII Timing – Data Input to MII ..........................................................................................................................78
Figure 19. PHY-Mode MII Timing – Data Received from MII ...............................................................................................................79
Figure 20. PHY-Mode MII Timing – Data Input to MII...........................................................................................................................79
Figure 21. SPI Input Timing....................................................................................................................................................................81
Figure 22. SPI Output Timing.................................................................................................................................................................82
Figure 23. Reset Timing .........................................................................................................................................................................83
128-Pin PQFP Package...........................................................................................................................................................................86
List of Tables
Table 1. FX and TX Mode Selection ......................................................................................................................................................22
Table 2. MDI/MDI-X Pin Definitions........................................................................................................................................................23
Table 3. MII Signals .................................................................................................................................................................................31
Table 4. SNI Signals ................................................................................................................................................................................32
Table 5. MII Management Interface Frame Format ..............................................................................................................................33
Table 6. Serial Management Interface (SMI) Frame Format................................................................................................................33
Table 7. Upstream Special Tagging Mode Format ..............................................................................................................................35
Table 8. STPID Egress Rules (Switch Port 3 to Processor)................................................................................................................35
Table 9. FID+DA Lookup in VLAN Mode ...............................................................................................................................................37
Table 10. FID+SA Lookup in VLAN Mode .............................................................................................................................................37
Table 11. KSZ8993M SPI Connections..................................................................................................................................................41
Table 12. Format of Static MAC Table (8 Entries)................................................................................................................................67
Table 13. Format of Static VLAN Table (16 Entries) ............................................................................................................................69
Table 14. Format of Dynamic MAC Address Table (1K Entries) ........................................................................................................69
Table 15. Format of “Per Port” MIB Counters......................................................................................................................................70
Table 16. Port 1s “Per Port” MIB Counters Indirect Memory Offsets................................................................................................71
Table 17. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets...............................................................................................72
Table 18. Format of “All Port Dropped Packet” MIB Counters ..........................................................................................................72
Table 19. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets .................................................................................72
Table 20. EEPROM Timing Parameters ................................................................................................................................................77
Table 21. SNI Timing Parameters ..........................................................................................................................................................78
Table 22. MAC-Mode MII Timing Parameters .......................................................................................................................................79
Table 23. PHY-Mode MII Timing Parameters ........................................................................................................................................80
Table 24. SPI Input Timing Parameters ................................................................................................................................................81
Table 25. SPI Output Timing Parameters .............................................................................................................................................82
Table 26. Reset Timing Parameters ......................................................................................................................................................83
Table 27. Transformer Selection Criteria..............................................................................................................................................85
Table 28. Qualified Single Port Magnetics ...........................................................................................................................................85
Table 29. Typical Reference Crystal Characteristics ..........................................................................................................................85
Micrel, Inc.
October 2008
9
M9999-020606
KSZ8993M/ML