NDS9959 Fairchild Semiconductor, NDS9959 Datasheet

MOSFET 2N-CH 50V 2A 8-SOIC

NDS9959

Manufacturer Part Number
NDS9959
Description
MOSFET 2N-CH 50V 2A 8-SOIC
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of NDS9959

Fet Type
2 N-Channel (Dual)
Fet Feature
Standard
Rds On (max) @ Id, Vgs
300 mOhm @ 1.5A, 10V
Drain To Source Voltage (vdss)
50V
Current - Continuous Drain (id) @ 25° C
2A
Vgs(th) (max) @ Id
4V @ 250µA
Gate Charge (qg) @ Vgs
15nC @ 10V
Input Capacitance (ciss) @ Vds
250pF @ 25V
Power - Max
900mW
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Configuration
Dual Dual Drain
Transistor Polarity
Dual N-Channel
Resistance Drain-source Rds (on)
0.3 Ohms
Forward Transconductance Gfs (max / Min)
2.7 S
Drain-source Breakdown Voltage
50 V
Gate-source Breakdown Voltage
+/- 20 V
Continuous Drain Current
+/- 2 A
Power Dissipation
2 W
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NDS9959TR

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_________________________________________________________________________________
Symbol
V
V
I
P
T
THERMAL CHARACTERISTICS
R
R
Absolute Maximum Ratings
© 1997 Fairchild Semiconductor Corporation
D
J
DSS
GSS
D
NDS9959
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage applications such
as DC motor control and DC/DC conversion where fast
switching, low in-line power loss, and resistance to transients
are needed.
,T
JA
JC
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous @ T
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
Operating and Storage Temperature Range
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
- Continuous @ T
- Pulsed
@ T
A
A
= 25°C
= 70°C
A
T
= 25°C
A
= 25°C unless otherwise noted
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1)
(Note 1a)
(Note 1a)
(Note 1a)
Features
2.0A, 50V. R
High density cell design for extremely low R
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
6
5
8
7
DS(ON)
NDS9959
-55 to 150
= 0.3
± 2.0
± 1.6
± 20
± 8
1.6
0.9
50
78
40
2
1
@ V
GS
= 10V
4
3
2
1
DS(ON)
February 1996
.
NDS9959.SAM
Units
°C/W
°C/W
W
°C
V
V
A

Related parts for NDS9959

NDS9959 Summary of contents

Page 1

... Dual MOSFET in surface mount package 25°C unless otherwise noted A = 25°C (Note 1a 70°C (Note 1a 25°C A (Note 1a) (Note 1b) (Note 1c) (Note 1a) (Note 1) February 1996 = 0 10V DS(ON) GS DS(ON NDS9959 50 ± 20 ± 2.0 ± 1.6 ± 1.6 1 0.9 -55 to 150 Units °C °C/W °C/W NDS9959.SAM ...

Page 2

... D(off) t Turn - Off Fall Time f Q Total Gate Charge g Q Gate-Source Charge gs Q Gate-Drain Charge gd Conditions 250 µ 55° - 250 µ 1.0 MHz 0 GEN 1 Min Typ Max Units µA 25 µA 100 nA -100 0.3 0 2.7 S 152 250 100 4 1.1 nC 1.5 nC NDS9959.SAM ...

Page 3

... C/W when mounted on a 0.003 in pad of 2oz cpper. 1a Scale letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. Conditions 1.25 A (Note 0V 1. /dt = 100 A/µ Min Typ Max Units 1.8 0.84 1.2 100 is guaranteed NDS9959.SAM ...

Page 4

... Figure 4. On-Resistance Variation with Drain 1 -55° 1 0.9 0.8 0.7 - Figure 6. Gate Threshold Variation with 7.0V 8.0V 9. DRAIN CURRENT (A) D Gate Voltage and Drain Current 125°C J 25°C -55° DRAIN CURRENT (A) D Current and Temperature 250µ JUNCTION TEMPERATURE (°C) J Temperature NDS9959.SAM ...

Page 5

... C rss Figure 10. Gate Charge Characteristics. t d(on OUT DUT Figure 12. Switching Waveforms V = 125°C J 25°C -55°C 0.4 0.6 0 BODY DIODE FORWARD VOLTAGE (V) SD Variation with Current and Temperature 10V GATE CHARGE (nC off t t d(off PULSE WIDTH 1.2 1 INVERTED NDS9959.SAM ...

Page 6

... Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. (continued -55° 25°C 0.5 125°C 0.1 0.05 0.01 0 Figure 14. Maximum Safe Operating Area. 0.01 0 TIME (sec 10V GS SINGLE PULSE T = 25°C A 0.2 0 DRAIN-SOURCE VOLTAGE ( ( See Note 1c JA P(pk ( Duty Cycle 100 300 NDS9959.SAM ...

Page 7

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ CMOS FACT™ FACT Quiet Series™ FAST FASTr™ GTO™ ...

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