ispPAC-CLK5304S-01T48I Lattice, ispPAC-CLK5304S-01T48I Datasheet - Page 35

• Manufacturer Part Number: ispPAC-CLK5304S-01T48I
• Description: Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
• Manufacturer: Lattice

Specifications of ispPAC-CLK5304S-01T48I

• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 85 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 30. PAC-Designer Design Entry Screen
In-System Programming
The ispClock5300S is an In-System Programmable (ISP™) device. This is accomplished by integrating all
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E
CMOS configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant
serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored
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on-chip, in non-volatile E
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all
ispClock5300S instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
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A user electronic signature (UES) feature is included in the E
CMOS memory of the ispClock5300S. This consists
of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory
control data. The specifics this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispClock5300S device to prevent unauthorized readout
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of the E
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional
user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can
not be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in
the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
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