CY28447LFXC Silicon Laboratories Inc, CY28447LFXC Datasheet - Page 9

• Manufacturer Part Number: CY28447LFXC
• Description: Clock Generators & Support Products Calistoga System Clk Extra SRC Output
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28447LFXC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 20, 2006
Byte 12: Control Register 12
Byte 13: Control Register 13
Table 5. Crystal Recommendations
The CY28447 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28447 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
14.31818 MHz
Frequency
Bit
Bit
(Fund)
@Pup
@Pup
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Cut
AT
CLKREQ#9
CLKREQ#8
CLKREQ#7
CLKREQ#6
CLKREQ#5
CLKREQ#4
CLKREQ#3
CLKREQ#2
Loading Load Cap
LCD 96_100M Clock
Parallel
RESERVED
RESERVED
CLKREQ#1
Speed
Name
Name
PCI4
PCI3
PCI2
PCI1
20 pF
0.1 mW
CLKREQ#9 Input Enable
0 = Disable 1 = Enable
CLKREQ#8 Input Enable
0 = Disable 1 = Enable
CLKREQ#7 Input Enable
0 = Disable 1 = Enable
CLKREQ#6 Input Enable
0 = Disable 1 = Enable
CLKREQ#5 Input Enable
0 = Disable 1 = Enable
CLKREQ#4 Input Enable
0 = Disable 1 = Enable
CLKREQ#3 Input Enable
0 = Disable 1 = Enable
CLKREQ#2 Input Enable
0 = Disable 1 = Enable
CLKREQ#1 Input Enable
0 = Disable 1 = Enable
LCD 96_100M Clock Speed
0 = 96 MHz 1 = 100 MHz
RESERVED, Set = 1
RESERVED, Set = 1
PCI4 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI3 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI2 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI1 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
(max.)
Drive
Shunt Cap
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
(max.)
5 pF
Motional
0.016 pF
(max.)
Description
Description
Tolerance
35 ppm
(max.)
Stability
30 ppm
(max.)
CY28447
Page 9 of 21
Aging
(max.)
5 ppm