78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 30

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

78Q8430 Data Sheet
Snooping the contents of a frame before it is read out of the receive QUE can be useful if additional
inspection of the frame is needed, beyond what is provided by classification, to determine the disposition
of a received frame. It can also be used, in conjunction with the QUE transfer feature, to minimize host
bus overhead in responding to simple ARP or ICMP requests. In this case, the host can use the Snoop
Interface to modify a received ARP or ICMP request and convert it into the appropriate response, while
the frame is still resident in the receive QUE. The QUE Transfer feature is then used to transfer the
response directly to a TX QUE and transmit it back to the source without having to read the entire frame
into host memory.
6.5
The Timers module (see
There are three watermarks (Interrupt, PAUSE and Headroom), accessed via the Water Mark Values
Register (WMVR), which can be used to manage memory usage based on the size of the free memory pool.
6.5.1
When the number of free BLOCKs falls below the interrupt threshold, the WATER MARK interrupt in the
HIR is triggered. An interrupt threshold setting of zero disables this feature.
6.5.2
When the number of free BLOCKs falls below the pause threshold, the QDR bit for the PAUSE QUE
triggers the transmission of the pause frame. A pause threshold setting of zero disables this feature.
6.5.3
When the number of free BLOCKs falls below the headroom threshold then the MAC receiver is halted
causing the MAC to drop any frames received after completion of the current frame. This condition is
cleared once the number of free BLOCKs rises back above the threshold. This prevents a saturated
receiver from consuming all free memory thereby locking out the local transmitter. A headroom setting of
zero disables this feature.
6.6
A block of hardware counters is implemented to allow monitoring transmit and receive statistics. These
counters are accessed and managed by using the Count Data Register (CDR), the Counter Control
Register (CCR) and the Counter Management Register (CMR).
6.6.1
Table 23 provides a summary of all counters by address. Counters at addresses 0x00 through 0x0E are
transmit counters. Counters at addresses 0x0F through 0x27 are receive counters.
30
Counter
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Water Marking
Counters
Interrupt Watermark
PAUSE Watermark
Headroom Watermark
Summary of Counters
Transmitted Packets, 0 Collisions, not deferred or excessive deferred
Transmitted Packets, 1 Collision
Transmitted Packets, 2-15 Collisions
Excessive Collisions
Deferred transmissions
Late Collisions
MAC errors (TX under-run or transmit halted)
Lost carrier sense errors
Excessive deferrals
Total packets transmitted
Multicast packets
Section
6.8) monitors the number of free memory blocks in the system input.
Table 23: Counter Summary
Counter Description
DS_8430_001
Rev. 1.2