78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 65

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

DS_8430_001
7.6.19 Count Data Register
7.6.20 Counter Control Register
Rev. 1.2
6
5
4
3
2
1
0
Name: CDR
Bits
31:0
Name: CCR
Bits
31:11
10
9
8
7:6
5:0
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
Default
Default
Reset Val: 0x0000_0000
Reset Val: 0x0000_0000
1
0
1
0
0
0
0
FullDup
1 = Full Duplex
0 = Half Duplex
The default setting for the MAC is full duplex mode. This bit needs to
be updated each time there is a link status change in the PHY.
SQE
Enable SQE checking.
No Ex Diff
Disable checking for excessive deferrals.
Reserved
Reserved
No Rx CRC
When this bit is set, the MAC receiver will strip the CRC bytes from the
end of received frames after the CRC check is complete.
No CRC Chk
When this bit is set, CRC checking is disabled. This bit should never be
set when the No Rx CRC bit is set as there will be no way to verify the
CRC.
Description
Count
Value of the counter indicated by CCR.
Description
Reserved
Auto Increment
When this bit is set, the address of the counter being accessed is
automatically incremented after each access to the CDR.
Clear on Read
When this bit is set, the counter being read is automatically cleared to
zero after each access to the CDR.
Access Mode
When this bit is clear, the CDR is in read mode. When set, the CDR is
in write mode.
Reserved
Address
Address of the counter to access. (00 to 0E, Transmit Counters; 0F to
25, Receive Counters)
Block: CTL
Block: CTL
Address: 0x164
Address: 0x168
78Q8430 Data Sheet
65