78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 64

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

78Q8430 Data Sheet
7.6.17 PROM Control Register
7.6.18 MAC Control Register
64
Name: PRCR
Bits
31:9
8
7:6
5:0
Name: MCR
Bits
31:28
27
26
25
24
23
22
21
20:18
17
16
15:8
7
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
Default
Default
0x000
0000
0x00
0000
0000
Reset Val: 0x0000_0000
Reset Val: 0x0080_0050
0x0
0
0
0
0
0
1
0
0
0
0
0
Description
Reserved
Busy
Writing a 1 initiates the EEPROM data transfer. The hardware will clear
the bit when the operation completes.
Operation
1 1 = Erase.
1 0 = Read.
0 1 = Write.
0 0 = Enable or Disable Writing, as specified in PROM Addr:
PROM Addr
Address of the EEPROM to access.
Description
Reserved
Tx Enable
When this bit is clear transmitting stops immediately.
Tx Halt
When this bit is set transmitting stops at the end of the current frame.
Rx Enable
When this bit is clear receiving stops immediately.
Rx Halt
When this bit is set receiving stops at the end of the current frame.
Rx Drop Error
When this bit is set then an error in the first 256 bytes will cause a
packet to be dropped. If clear, error packets are forwarded to the host.
Keep Dropped Status
Normally, the status for a dropped frame is not added to the receive
status FIFO. When this bit is set then a status for all frames, including
dropped frames, is added to the receive status FIFO. The status for a
dropped frame will have a size of zero in the RPSR.
Jumbo OK
Normally frames in excess of the maximum allowed by 802.3 are
flagged as bad. If this bit is set then larger frame sizes are allowed.
Reserved
MACRST
Software re-initialization. Setting this bit will also automatically set both
Rx and Tx Halt bits and clear both Rx and Tx Enable bits. This bit is
only cleared by writing a zero.
MACLOOP
Loopback mode for the MAC.
Reserved
No Rx PAD
Strip the padding bytes from the end of received frames that are 64
bytes in length. When the padding is stripped from a frame the CRC is
stripped as well.
[5:4] = 11, Enable
[5:4] = 00, Disable
Block: CTL
Block: CTL
Address: 0x14C
Address: 0x154
DS_8430_001
Rev. 1.2