78Q8430-100CGTR/F Maxim Integrated Products, 78Q8430-100CGTR/F Datasheet - Page 42

• Manufacturer Part Number: 78Q8430-100CGTR/F
• Description: Telecom ICs 10/100MAC+PHY MULTI MEDIA OFFLOAD CNTRLR
• Manufacturer: Maxim Integrated Products

78Q8430 Data Sheet
6.7.4.2
Source address filtering can be used to drop frames with a specific address while passing all others.
Table 30 contains the rules on processing source address.
6.7.4.3
Table 31 contains the rules on processing length/type, MAC control frames and start IP header checksum
check.
6.7.4.4
The packet classification engine can use the WAKE action to signal the host to come out of power down
mode. This is used to implement the Wake-On-LAN feature.
The Power Management Control and Status Register (PMCSR) is used to control the hardware response
to a WAKE action. If the PS field of the PMCSR is zero then all WAKE actions are ignored. The
WAKE action is only honored if the part is currently in a power down mode as determined by the
PS field. If the PME_ENB bit in the PMCSR is set then a valid WAKE action will trigger the assertion of
the PMEB primary output. If the PME_ENB bit is clear then a valid WAKE action will only result in the
normal HIR WAKE interrupt.
When the host is notified of a valid WAKE event, either by the assertion of the PMEB primary output or
assertion of INTB via the WAKE HIR interrupt, the rule that triggered the event can be read from the
Wake Up Status Register (WUSR). A valid WAKE event will also start the Host Not Responding (HNR)
timer. When the host is notified of a WAKE event, it must clear the event by setting the PME bit in the
42
Rule#
Rule#
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
Table 31: Process Length/Type, MAC Control Frames and Start IP Header Checksum Rules
PrevHit
Source Address Filtering
Length/Type Field, MAC Control Frames and IP Header Checksum
Wake on LAN
0x30
0x30
0x2B
0x00
0x2E
0x2B
0x2F
0x29
0x29
0x2F
0x26
0x25
0x24
0x28
0x28
0x22
0x22
0x20
0x1E
0x1D
0x1D
PrevHit
PH-Mask
PH-Mask
0x70
0x70
0x7F
0x00
0x7F
0x7F
0x7C
0x7F
0x7F
0x7C
0x7F
0x7F
0x7E
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
0x7F
Table 30: Process Source Address Rules
0x01
0x00
Data
Data
0x00
0x00
0x81
0x00
0x88
0x08
0x00
0x00
0x00
0x40
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x3D
0x00
D-Mask
0x01
0x00
D-Mask Next
0xFF
0x00
0xFF
0x00
0xFF
0xFF
0x00
0x00
0x00
0xF0
0x00
0xFF
0x00
0xFF
0x00
0x00
0x00
0xFF
0x00
DROP 0x00
MD
DONE 0x00
MD
DONE 0x00
MD
MD
DONE 0x00
MD
MD
MD
MD
MD
DONE 0x00
MD
DONE 0x00
MD
MX
DONE 0x00
DONE 0x00
MD
Next
0x05
Offset
Offset Action
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x3F
0x00
0x00
0x00
0x00
NOP
NOP
Action
VLAN
NOP
TDLTH
TDLTL
TDLTH
MCTL
TDLTL
TDLTH
TDLTL
IPCK
TXA
NOP
NOP
NOP
NOP
TDPH
TDPL
PAUSE
NOP
Interrupt Comment
0
0
Interrupt Comment
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MC drop
pass other
MCTL pause
MCTL other
MCTL pause
with bad SRC
DS_8430_001
Rev. 1.2