LAN91C110-PU SMSC, LAN91C110-PU Datasheet - Page 13

• Manufacturer Part Number: LAN91C110-PU
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C110-PU

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2.6
SMSC LAN91C110 Rev. B
Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will be
present at RXD0-RXD3 when RX_DV is activated. The LAN91C110 requires no training sequence beyond
a full flag octet for reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising edges. RXD0
carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV goes inactive when
the last valid nibble of the packet (CRC) is presented at RXD0-RXD3.
RX_ER might be asserted during packet reception to signal the LAN91C110 that the present receive packet
is invalid. The LAN91C110 will discard the packet by treating it as a CRC error.
RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not
consider misaligned cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on
non-preamble patterns.
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and backoff
functions), but it is not used for receive framing functions. CRS100 is an asynchronous signal and it will be
active whenever there is activity on the cable, including LAN91C110 transmissions and collisions.
The MII SELECT bit in the CONFIG REGISTER must always be set for proper chip function.
Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running
clocks. The LAN91C110 will not rely on the presence of TX25 and RX25 during reset and will use its own
internal clock whenever a timeout on TX25 is detected.
MII Management Interface Block
PHY management through the MII management interface is supported by the LAN91C110 by providing the
means to drive a tri-statable data output, a clock, and reading an input. Timing and framing for each
management command is to be generated by the CPU.
DATASHEET
Page 13
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Revision 1.0 (11-04-08)
Datasheet