LAN8187-JT SMSC, LAN8187-JT Datasheet
LAN8187-JT
Specifications of LAN8187-JT
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LAN8187-JT Summary of contents
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... Vendor Specific register functions Low profile 64-pin TQFP lead-free RoHS compliant package ( 1.4mm) 4 LED status indicators Commercial Operating Temperature 0° 70° C Industrial Operating Temperature -40° 85° C version available (LAN8187i) SMSC LAN8187/LAN8187i LAN8187/LAN8187i ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR ...
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... LAN8187-JT for 64-pin, TQFP lead-free RoHS compliant package LAN8187i-JT for (Industrial Temp) 64-pin, TQFP lead-free RoHS compliant package This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...
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... Re-starting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7.3 Disabling Auto-negotiation 4.7.4 Half vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.9 Internal +1.8V Regulator Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.1 Disable the Internal +1.8V Regulator 4.9.2 Enable the Internal +1.8V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.10 (TX_ER/TXD4)/nINT Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SMSC LAN8187/LAN8187i ® Technology 3 DATASHEET Revision 1.7 (03-04-11) ...
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... Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1 Magnetics Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.3 Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.4 Evaluation board Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Chapter 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 4 DATASHEET ® Technology Datasheet SMSC LAN8187/LAN8187i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Datasheet List of Figures Figure 1.1 LAN8187/LAN8187i System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 1.2 LAN8187/LAN8187i Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2.1 Package Pinout (Top View Figure 4.1 100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4.2 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4 ...
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... List of Tables Table 2.1 LAN8187/LAN8187i 64-PIN TQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.1 MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3.2 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.3 Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3.4 Boot Strap Configuration Inputs Table 3.5 General Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.6 10/100 Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.7 Analog References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3.8 No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3 ...
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... Table 6.8 10M RMII Receive Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 6.9 10M RMII Transmit Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 6.10 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 6.11 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 6.12 LAN8187/LAN8187i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 7.1 Maximum Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 7.2 ESD and LATCH-UP Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 7.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 7 ...
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... RMII requires only 6 pins for each MAC to PHY interface plus one common reference clock. The MII requires 16 pins for each MAC to PHY interface. The SMSC LAN8187/LAN8187i is capable of running in RMII mode. Please contact your SMSC sales representative for the latest RMII specification. ...
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... TX_EN 100M Rx TX_ER Logic TX_CLK RXD[0..3] RX_DV Receive Section RX_ER RX_CLK 10M Rx CRS Logic COL/CRS_DV MDC MDIO Figure 1.2 LAN8187/LAN8187i Architectural Overview SMSC LAN8187/LAN8187i ® Technology 10M Tx 10M Logic Transmitter Transmit Section 100M Tx 100M Logic Transmitter DSP System: Analog-to- Clock Digital ...
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... Figure 2.1 Package Pinout (Top View) 10 DATASHEET ® Technology Datasheet 48 CRS COL/CRS_DV 48 CRS nINT/TX_ER/TXD4 COL/CRS_DV TXD3 nINT/TX_ER/TXD4 TXD2 TXD3 VDDIO TXD2 TXD1 VDDIO TXD0 TXD1 VSS5 TXD0 TX_EN VSS5 TX_CLK TX_EN AMDIX_EN TX_CLK CH_SELECT AMDIX_EN RX_ER/RXD4 CH_SELECT RX_CLK RX_ER/RXD4 33 RX_DV RX_CLK 33 RX_DV SMSC LAN8187/LAN8187i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Datasheet Table 2.1 LAN8187/LAN8187i 64-PIN TQFP Pinout PIN NO. PIN NAME 1 GPO0/RMII 2 GPO1/PHYAD4 3 GPO2 4 MODE0 5 MODE1 6 MODE2 7 VSS1 VSS7 10 VSS8 VDD33 14 VDD_CORE 15 VSS2 16 SPEED100/PHYAD0 17 LINK/PHYAD1 ACTIVITY/PHYAD2 20 FDUPLEX/PHYAD3 XTAL2 23 CLKIN/XTAL1 24 VSS3 25 nRST ...
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... I Transmit Enable: Indicates that valid data is presented on the TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0] have valid data. O Transmit Clock: 25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode. Note: This signal is not used in RMII Mode 12 DATASHEET ® Technology Datasheet SMSC LAN8187/LAN8187i ...
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... SIGNAL NAME RXD0 RXD1 RXD2 RXD3/ nINTSEL RX_ER/ RXD4 RX_CLK COL/CRS_DV SMSC LAN8187/LAN8187i ® Technology Table 3.1 MII Signals (continued) TYPE DESCRIPTION O Receive Data 0: Bit 0 of the 4 data bits that are sent by the PHY in the receive path. O Receive Data 1: Bit 1 of the 4 data bits that are sent by the PHY in the receive path ...
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... This signal is mux’d with ACTIVITY I/O PHY Address Bit 1: set the default address of the PHY. Note: This signal is mux’d with LINK I/O PHY Address Bit 0: set the default address of the PHY. Note: This signal is mux’d with SPEED100 14 DATASHEET ® Technology Datasheet a SMSC LAN8187/LAN8187i ...
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... MODE2 MODE1 MODE0 REG_EN AMDIX_EN CH_SELECT GPO0/RMII a.On nRST transition high, the PHY latches the state of the configuration pins in this table. SMSC LAN8187/LAN8187i ® Technology TYPE DESCRIPTION I PHY Operating Mode Bit 2: set the default MODE of the PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page the MODE options ...
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... Section 4.6.3, "MII vs. RMII Configuration," on page 26 for more details. Table 3.6 10/100 Line Interface TYPE DESCRIPTION AO Transmit Data: 100Base-TX or 10Base-T differential transmit outputs to magnetics. AO Transmit Data: 100Base-TX or 10Base-T differential transmit outputs to magnetics. 16 DATASHEET ® Technology Datasheet Section 5.4.9.2. Table 4.4, SMSC LAN8187/LAN8187i ...
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... EXRES1 SIGNAL NAME NC SIGNAL NAME AVDD[1-3] AVSS[1-4] VDD_CORE VDD33 VDDIO VSS[1-8] SMSC LAN8187/LAN8187i ® Technology Table 3.6 10/100 Line Interface AI Receive Data: 100Base-TX or 10Base-T differential receive inputs from magnetics. AI Receive Data: 100Base-TX or 10Base-T differential receive inputs from magnetics. Table 3.7 Analog References ...
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... Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR its ria rive Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 18 DATASHEET ® Technology Datasheet S cra its tic s Table 4.1. Each 4-bit data-nibble SMSC LAN8187/LAN8187i ...
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... Second nibble of ESD, causes deassertion of CRS if following /T/, else assertion of RX_ER 00100 H Transmit Error Symbol 00110 V INVALID, RX_ER if during RX_DV 11001 V INVALID, RX_ER if during RX_DV SMSC LAN8187/LAN8187i ® Technology Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 ...
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... Transmitter. Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 20 DATASHEET ® Technology Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID SMSC LAN8187/LAN8187i ...
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... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN8187/LAN8187i ® Technology 100M PLL ...
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... RXD Figure 4.3 Relationship Between Received Data and specific MII Signals Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR data data data data data data data data 22 DATASHEET ® Technology Datasheet T R Idle SMSC LAN8187/LAN8187i ...
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... Detect," on page For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the LAN8187/LAN8187i. TXD[1:0] shall be “00” to indicate idle when TX_EN is deasserted. Values of TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signalling (to be defined). Values other than “ ...
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... For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge of the RMII REF_CLK. Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR 24 DATASHEET ® Technology Datasheet SMSC LAN8187/LAN8187i ...
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... RMII The SMSC LAN8187/LAN8187i supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase ...
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... MII vs. RMII Configuration The LAN8187/LAN8187i must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done through the GPO0/RMII pin. To select MII mode, float the GPO0/RMII pin. To select RMII mode, pull-high with an external resistor (see Resistors,” ...
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... The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller. The advertised capabilities of the PHY are stored in register 4 of the SMI registers. The default advertised by the PHY is determined by user-defined on-chip signal options. SMSC LAN8187/LAN8187i ® Technology Table 4.2 MII/RMII Signal Mapping ...
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... Register 0, bit 9 must be set before the new abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN8187/LAN8187i does not support “Next Page” capability. Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR ...
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... Parallel Detection If the LAN8187/LAN8187i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard. ...
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... Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Table 4.3 Auto-MDIX Control EXTERNAL PINS CH_SELECT DATASHEET ® Technology Datasheet STATUS TX AND RX OUTPUT PINS Auto-MDIX Normal MDI Crossed MDIX Auto-MDIX Normal MDI Crossed MDIX SMSC LAN8187/LAN8187i ...
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... Both a 4.7uF low-ESR and a 0.1uF capacitor must be added at the VDD_CORE pin and placed close to the PHY. This capacitance ensures stability of the internal regulator. SMSC LAN8187/LAN8187i ® Technology 33) is attached from REG_EN to VSS. When both VDDIO and VDDA Section 4 ...
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... Variable Voltage I/O The Digital I/O pins on the LAN8187/LAN8187i are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1. +3.6V. Due to this low voltage feature addition, the system designer needs to take consideration as for two aspects of their design ...
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... Interrupt 4.13.1 Serial Management Interface (SMI) The Serial Management Interface is used to control the LAN8187/LAN8187i and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers allowed by the specification. Non-supported registers (7 to 15) will be read as hexadecimal “ ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Read Cycle PHY Address Register Address Data To Phy Write Cycle PHY Address Register Address Data To Phy 34 DATASHEET ® Technology Datasheet ... ... D1 D15 D14 D0 Turn Data Around Data From Phy ... ... D15 D14 D1 D0 Turn Data Around SMSC LAN8187/LAN8187i ...
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Chapter 5 Registers Reset Loopback Speed Select A/N Enable 100Base- 100Base-TX 100Base-TX 10Base-T T4 Full Duplex Half Duplex Full Duplex PHY ID Number (Bits 3-18 of the Organizationally ...
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Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended Next Acknowledge Remote Reserved Page Fault Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended Reserved Table 5.8 ...
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Table 5.11 Register 10 (Extended ...
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Reserved RSVD EDPWRDOWN RSVD LOWSQEN RSVD = Reserved Reserved MIIMODE Table 5.17 Silicon Revision Register 16: Vendor-Specific ...
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Table 5.24 Special Control/Status Indications Register 27: Vendor-Specific AMDIXCTRL Reserved CH_SELECT Table 5.25 Special Internal Testability Control Register 28: Vendor-Specific Table 5.26 ...
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Table 5.28 PHY Special Control/Status Register 31: Vendor-Specific Reserved Autodone Reserved GPO2 GPO1 GPO0 Enable 4B5B Reserved Speed Indication Reserved Scramble Disable 0 ...
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... The mode key is as follows Read/write Self clearing Write only Read only Latch high, clear on read of register Latch low, clear on read of register, NASR = Not Affected by Software Reset X = Either SMSC LAN8187/LAN8187i ® Technology Table 5.29 SMI Register Mapping DESCRIPTION 41 DATASHEET Group Basic ...
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... Table 5.31 Register 1 - Basic Status DESCRIPTION 42 DATASHEET ® Technology Datasheet MODE DEFAULT RW Set by MODE[2:0] bus RW Set by MODE[2:0] bus Set by MODE[2:0] bus RW Set by MODE[2:0] bus MODE DEFAULT SMSC LAN8187/LAN8187i ...
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... Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved 4.11:10 Pause Operation SMSC LAN8187/LAN8187i ® Technology DESCRIPTION Table 5.32 Register 2 - PHY Identifier 1 DESCRIPTION Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. OUI=00800Fh Table 5.33 Register 3 - PHY Identifier 2 ...
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... TX full duplex ability able ability 1 = 10Mbps with full duplex 10Mbps with full duplex ability 1 = 10Mbps able 10Mbps ability [00001] = IEEE 802.3 44 DATASHEET ® Technology Datasheet MODE DEFAULT Set by MODE[2:0] bus Set by MODE[2:0] bus RW Set by MODE[2:0] bus RW 00001 MODE DEFAULT 00001 SMSC LAN8187/LAN8187i ...
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... LOWSQEN 17.10 MDPREBP 17.9 FARLOOPBACK 17.8:7 Reserved SMSC LAN8187/LAN8187i ® Technology DESCRIPTION 1 = fault detected by parallel detection logic fault detected by parallel detection logic 1 = link partner has next page ability 0 = link partner does not have next page ability 1 = local device has next page ability ...
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... Section 5.4.9.1, "Physical Address Bus - PHYAD[4:0]," on page 55 for more details. 46 DATASHEET ® Technology Datasheet MODE DEFAULT MODE DEFAULT RW 0 RW, Note 5.1 NASR RW, 000000 NASR RW, XXX for more NASR EVB8700 default 111 RW, PHYAD NASR EVB8700 default 11111 for additional information. SMSC LAN8187/LAN8187i ...
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... Reserved Table 5.42 Register 28 - Special Internal Testability Controls ADDRESS NAME 28.15:0 Reserved SMSC LAN8187/LAN8187i ® Technology DESCRIPTION 100Base-TX receiver-based error register that increments when an invalid code symbol is received including IDLE symbols. The counter is incremented only once per packet, even when the received packet contains more than one symbol error ...
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... Do not write to this register. Ignore on read. Must be set to 0 Auto-negotiation done indication Auto-negotiation is not done or disabled (or not active Auto-negotiation is done Write as 0, ignore on Read. Reserved 48 DATASHEET ® Technology Datasheet MODE DEFAULT MODE DEFAULT MODE DEFAULT SMSC LAN8187/LAN8187i ...
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... It generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the Interrupt Mask Register 30. The Interrupt system on the SMSC LAN8187/8187i has two modes, a Primary Interrupt mode and an Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set, the difference is how they de-assert the output interrupt signal nINT ...
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... Falling 6.4 or Reading register 6, or Reading register 29 or Re-AutoNegotiate or Link down Rising 6.1 Falling of 6.1 or Reading register 6, or Reading register 29 Re-AutoNegotiate, or Link Down. Table 5.47). Condition to Bit to Clear nINT De-Assert. nINT 17.1 low 29.7 Rising 1.5 1.5 low 29.6 SMSC LAN8187/LAN8187i ...
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... In 10M mode, COL pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de- assertion of TX_EN). This is the Signal Quality Error (SQE) signal and indicates that the transmission was successful. The user can disable this pulse by setting bit 11 in register 27. SMSC LAN8187/LAN8187i ® Technology 1 ...
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... Link Integrity Test The LAN8187/LAN8187i performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Management Register 1, and is driven to the LINK LED. ...
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... The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address latched in on reset. The LAN8187/LAN8187i senses each Phy address bit and changes the polarity of the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active- low. If the address bit is set as level “ ...
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... The Full-Duplex LED output is driven active low when the link is operating in Full-Duplex mode. 5.4.8 Loopback Operation The LAN8187/LAN8187i may be configured for near-end loopback and far loopback. 5.4.8.1 Near-end Loopback Near-end loopback is a mode that sends the digital transmit data back out the receive data signals for testing purposes as indicated by the blue arrows in by setting bit register 0 bit 14 to logic one ...
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... Figure 5.3 Far Loopback Block Diagram 5.4.8.3 Connector Loopback The LAN8187/LAN8187i maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown in transmit signals an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and 100. ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Table 5.48 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES REGISTER 0 [13,12,10,8] 0000 0001 1000 1001 1100 1100 N/A X10X 56 DATASHEET ® Technology Datasheet REGISTER 4 [8,7,6,5] N/A N/A N/A N/A 0100 0100 N/A 1111 SMSC LAN8187/LAN8187i ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR Datasheet Chapter 6 AC Electrical Characteristics The timing diagrams and limits in this section define the requirements placed on the external signals of the LAN8187/LAN8187i. 6.1 Serial Management Interface (SMI) Timing The Serial Management Interface is used for status and control as described in ...
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... Receive signals hold from RX_CLK rising RX_CLK frequency RX_CLK Duty-Cycle Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 2.1 2.2 Valid Data MIN TYP DATASHEET ® Technology Datasheet MAX UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187i ...
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... Figure 6.3 100M MII Transmit Timing Diagram Table 6.3 100M MII Transmit Timing Values PARAMETER DESCRIPTION T3.1 Transmit signals required setup to TX_CLK rising Transmit signals required hold after TX_CLK rising TX_CLK frequency TX_CLK Duty-Cycle SMSC LAN8187/LAN8187i ® Technology T 3.1 Valid Data MIN TYP MAX 12 0 ...
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... Receive signals hold from RX_CLK rising RX_CLK frequency RX_CLK Duty-Cycle Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T T 4.1 4.2 Valid Data MIN TYP DATASHEET ® Technology Datasheet MAX UNITS NOTES ns ns MHz % SMSC LAN8187/LAN8187i ...
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... Figure 6.5 10M MII Transmit Timing Diagrams Table 6.5 10M MII Transmit Timing Values PARAMETER DESCRIPTION T5.1 Transmit signals required setup to TX_CLK rising Transmit signals required hold after TX_CLK rising TX_CLK frequency TX_CLK Duty-Cycle SMSC LAN8187/LAN8187i ® Technology T 5.1 Valid Data MIN TYP MAX ...
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... Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 6.1 Valid Data MIN TYP MAX DATASHEET ® Technology Datasheet UNITS NOTES ns MHz SMSC LAN8187/LAN8187i ...
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... Figure 6.7 100M RMII Transmit Timing Diagram Table 6.7 100M RMII Transmit Timing Values PARAMETER DESCRIPTION T8.1 Transmit signals required setup to rising edge of CLKIN T8.2 Transmit signals required hold after rising edge of REF_CLK CLKIN frequency SMSC LAN8187/LAN8187i ® Technology T T 8.1 8.2 Valid Data MIN TYP MAX 2 1 ...
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... Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency Revision 1.7 (03-04-11) ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 9.1 Valid Data MIN TYP MAX DATASHEET ® Technology Datasheet UNITS NOTES ns MHz SMSC LAN8187/LAN8187i ...
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... REF_CLK CLKIN frequency 6.4 RMII CLKIN Timing Table 6.10 RMII CLKIN (REF_CLK) Timing Values PARAMETER DESCRIPTION CLKIN frequency CLKIN Frequency Drift CLKIN Duty Cycle CLKIN Jitter SMSC LAN8187/LAN8187i ® Technology T T 10.1 10.2 Valid Data MIN TYP MAX ...
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... ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR T 11 11.2 11.3 T 11.4 Figure 6.10 Reset Timing Diagram Table 6.11 Reset Timing Values MIN TYP MAX 100 200 2 3 800 66 DATASHEET ® Technology Datasheet UNITS NOTES clock cycles for 25 MHz clock or 40 clock cycles for 50MHz clock SMSC LAN8187/LAN8187i ...
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... Datasheet 6.6 Clock Circuit LAN8187/LAN8187i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input for operation in MII mode. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. The user is required to supply a 50MHz single-ended clock for RMII operation. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum ...
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... PARAMETER CONDITIONS Power pins to all other pins. VDD33,VDDIO To VSS ground Digital IO VSS to all other pins VSS LAN8187-JT Operating Temperature LAN8187i-JT Operating Temperature Storage Temperature Table 7.2 ESD and LATCH-UP Performance ...
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... EN61000-4-2 specification without the need for additional board level protection. 7.1.2 Operating Conditions Table 7.3 Recommended Operating Conditions PARAMETER CONDITIONS VDD33 to VSS VDD33 INPUT VOLTAGE ON DIGITAL PINS VOLTAGE ON ANALOG I/O PINS (RXP, RXN) T LAN8187-JT A AMBIENT TEMPERATURE T LAN8187I- A AEZG SMSC LAN8187/LAN8187i ® Technology MIN TYP MAX UNITS 3 ...
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... Note 7.1 1.1 39 128.7 0.9 37 122.1 0.1 34.1 83.88 Note 7.1 0.5 13.85 45.7 0.4 13.0 42.9 0.3 12.4 37.02 Note 7.1 0.39 3.52 11.62 0.34 3.07 10.13 0.3 2.44 4.45 Note 7.1 SMSC LAN8187/LAN8187i ...
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... VDDIO TX_CLK RXD0 RXD1 RXD2 RXD3 RX_ER/RXD4 RX_DV RX_CLK CRS COL MDC 0.68 * VDDIO MDIO 0.68 * VDDIO nINT/TX_ER/TXD4 0.68 * VDDIO SMSC LAN8187/LAN8187i ® Technology Table 7.5 MII Bus Interface Signals 0.4 * VDDIO 0.4 * VDDIO 0.4 * VDDIO 0.4 * VDDIO 0.4 * VDDIO - ...
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... Table 7.13, 74 +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0 +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V VDDIO – +0.4 V +0.4 V 3.7 V +0.4 V VDDIO – +0.4 V SMSC LAN8187/LAN8187i ...
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... EXRES1 AI NC AI/O Table 7.11 Internal Pull-Up / Pull-Down Configurations NAME SPEED100/PHYAD0 LINK/PHYAD1 ACTIVITY/PHYAD2 FDUPLEX//PHYAD3 GPO1/PHYAD4 MODE0 MODE1 MODE2 nINT/TX_ER/TXD4 nRST RXD3/nINTSEL MDIO MDC RX_ER/RXD4 RX_DV GPO0/RMII SMSC LAN8187/LAN8187i ® Technology Table 7.9 General Signals 0.4 * VDDIO +0 Table 7.10 Analog References V V ...
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... RFS 1.4 SYMBOL MIN TYP V 2.2 2.5 OUT V 300 420 DS 74 DATASHEET ® Technology Datasheet UNITS NOTES mVpk Note 7.4 mVpk Note 7.4 % Note 7.4 nS Note 7.4 nS Note 7 Note 7 Note 7.6 MAX UNITS NOTES 2.8 V Note 7.7 585 mV SMSC LAN8187/LAN8187i ...
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... Suggested Magnetics”. http://www.smsc.com/main/anpdf/an813.pdf 8.2 Application Notes Application examples are given in pdf format on the SMSC LAN8187 web site. The link to the web site is shown below. http://www.smsc.com/main/catalog/lan8187.html Please check the web site periodically for the latest updates. ...
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... Integrated 3.3V Regulator APPLICATIONS The EVB8187 Evaluation board simplifies the process of testing and evaluating an Ethernet Connection in your application. The LAN8187 device is installed on the EVB board and all associated circuitry is included, along with all configuration options. The Benefits of adding an external MII interface are: ...
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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm per side. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN8187/LAN8187i ® Technology MAX REMARKS 1 ...
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... VDD_CORE are stable. Added Figure. Corrected bit value for Asymmetric and Symmetric PAUSE. Enhanced this section. Added information about register bit 18.14. First sentence of second paragraph changed: From: “between 35% and 65%” To: “between 40% and 60%“ 78 DATASHEET ® Technology Datasheet CORRECTION Section 4.6.3, 26. SMSC LAN8187/LAN8187i ...