LAN8187-JT SMSC, LAN8187-JT Datasheet - Page 31

• Manufacturer Part Number: LAN8187-JT
• Description: Ethernet ICs HiPerfrm Ethrnt PHY
• Manufacturer: SMSC
• Type: MII/RMII Ethernet Transceiverr

Specifications of LAN8187-JT

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 802.3ab
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
Datasheet
SMSC LAN8187/LAN8187i
4.9
4.9.1
4.9.2
One feature of the flexPWR technology is the ability to to configure the internal 1.8V regulator off.
When the regulator is disabled, external 1.8V must be supplied to VDD_CORE. This makes it possible
to reduce total system power, since an external switching regulator with greater efficiency than the
internal linear regulator may be used to provide the +1.8V to the PHY circuitry.
Disable the Internal +1.8V Regulator
To disable the +1.8V internal regulator, a pulldown strapping resistor (see
Configuration Resistors,” on page
are within specification, the PHY will sample the REG_EN pin to determine if the internal regulator
should turn on. If the pin is grounded to VSS, then the internal regulator is disabled, and the system
must supply +1.8V to the VDD_CORE pin. The voltage at VDD33 must be at least 2.64V (0.8 * 3.3V)
before voltage is applied to VDD_CORE. As descibed in
floating or pulled up to VDDIO, then the internal regulator is enabled and the system does not supply
+1.8V to the VDD_CORE pin.
When the +1.8V internal regulator is disabled, a 0.1uF capacitor must be added at the VDD_CORE
pin and placed close to the PHY. This capacitance provides decoupling of the external power supply
noise.
Enable the Internal +1.8V Regulator
To enable the internal regulator, a pull-up resistor (see
Resistors,” on page
floating, the internal regulator will aslo be enabled.
Both a 4.7uF low-ESR and a 0.1uF capacitor must be added at the VDD_CORE pin and placed close
to the PHY. This capacitance ensures stability of the internal regulator.
Internal +1.8V Regulator Disable
Figure 4.4 Direct cable connection vs. Cross-over cable connection.
33) to VDDIO may be added to the REG_EN pin. When the REG_EN pin is left
33) is attached from REG_EN to VSS. When both VDDIO and VDDA
DATASHEET
31
®
Technology
Section
Table 4.4, “Boot Strapping Configuration
4.9.2, when the REG_EN pin is left
Table 4.4, “Boot Strapping
Revision 1.7 (03-04-11)