DS2152LN Maxim Integrated Products, DS2152LN Datasheet - Page 55

• Manufacturer Part Number: DS2152LN
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS2152LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS2152
11 ELASTIC STORES OPERATION
The DS2152 contains dual two-frame (386 bits) elastic stores: one for the receive direction and one for
the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert
the T1 data stream to 2.048Mbps (or a multiple of 2.048Mbps), which is the E1 rate. Secondly, they can
be used to absorb the differences in frequency and phase between the T1 data stream and an
asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544MHz or 2.048MHz). The
backplane clock can burst at rates up to 8.192MHz. Both elastic stores contain fully controlled slip
capability, which is necessary for this second purpose. The receive side elastic store can be enabled via
CCR1.2 and the transmit side elastic store is enabled via CCR1.7. The elastic stores can be forced to a
known depth via the Elastic Store Reset bit (CCR3.6). Toggling the CCR3.6 bit forces the read and write
pointers into opposite frames. Both elastic stores within the DS2152 are fully independent and no
restrictions apply to the sourcing of the various clocks that are applied to them. The transmit side elastic
store can be enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each
elastic store can interface to either a 1.544MHz or 2.048MHz backplane without regard to the backplane
rate the other elastic store is interfacing.
11.1 Receive Side
If the receive side elastic store is enabled (CCR1.2 = 1), then the user must provide either a 1.544MHz
(CCR1.3 = 0) or 2.048MHz (CCR1.3 = 1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR2.3 = 1) or having the RSYNC pin provide a
pulse on frame boundaries (RCR2.3 = 0). If the user wishes to obtain pulses at the frame boundary, then
RCR2.4 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary, then
RCR2.4 must be set to 1. The DS2152 always indicates frame boundaries via the RFSYNC output
whether the elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will
be indicated via the RMSYNC output. If the user selects to apply a 2.048MHz clock to the RSYSCLK
pin, then the data output at RSER will be forced to all 1s every fourth channel and the F-bit will be placed
in the MSB bit position of channel 1. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8,
12, 16, 20, 24, and 28) are forced to 1. Also, in 2.048MHz applications, the RCHBLK output is forced
high during the same channels as the RSER pin. See Section
16
for more details. This is useful in T1 to
CEPT (E1) conversion applications. If the 386-bit elastic buffer either fills or empties, a controlled slip
occurs. If the buffer empties, a full frame of data (193 bits) is repeated at RSER, and the SR1.4 and
RIR1.3 bits are set to 1, except the MSB of channel 1. See
Figure
16-5. If the buffer fills, a full frame of
data is deleted, and the SR1.4 and RIR1.4 bits are set to 1.
11.2 Transmit Side
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR1.7. A 1.544MHz (CCR1.4 = 0) or 2.048MHz (CCR1.4 = 1) clock can be
applied to the TSYSCLK input. If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then
the data input at TSER will be ignored every fourth channel. Hence, channels 1, 5, 9, 13, 17, 21, 25, and
29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are ignored. The F-bit may be sampled at the MSB of
channel 1. See
Figure
16-10. The user must supply an 8kHz frame sync pulse to the TSSYNC input.
Also, in 2.048MHz applications the TCHBLK output is forced high during the channels ignored by the
DS2152. See Section
16
for more details. Controlled slips in the transmit elastic store are reported in the
RIR2.3 bit, and the direction of the slip is reported in the RIR2.5 and RIR2.4 bits.
55 of 97