DS2152LN Maxim Integrated Products, DS2152LN Datasheet - Page 67

• Manufacturer Part Number: DS2152LN
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated Products

Specifications of DS2152LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2 Legacy FDL Support
In order to provide backward compatibility to the older DS2151 device, the DS2152 maintains the
circuitry that existed in the previous generation of T1 single-chip transceivers. This section covers the
circuitry and operation of this legacy functionality. In new applications, it is recommended that the
HDLC controller and BOC controller described in Section
to have both the new HDLC/BOC controller and the legacy hardware working at the same time.
However, this is not possible on the transmit side since their can be only one source the of the FDL data
internal to the device.
12.2.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2ms (8 times 250µs). The
DS2152 will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user
has 2ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed
into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT pin will toggled
low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs
pattern until an important event occurs.
The DS2152 also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2152 will
automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will automatically
remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The
CCR2.0 bit should always be set to a 1 when the DS2152 is extracting the FDL. More on how to use the
DS2152 in FDL applications in this legacy support mode is covered in a separate application note.
RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
(MSB)
RFDL7
SYMBOL
RFDL7
RFDL0
RFDL6
POSITION
RFDL.7
RFDL.0
RFDL5
NAME AND DESCRIPTION
MSB of the Received FDL Code
LSB of the Received FDL Code
RFDL4
67 of 97
RFDL3
12.1
be used. On the receive side, it is possible
RFDL2
RFDL1
RFDL0
(LSB)