COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 3

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
4.2
4.3
4.4
4.5
4.6
Chapter 5
5.1
5.2
Chapter 6
6.1
6.2
6.3
SMSC COM20022I 3V
4.2.1
4.5.1
4.5.2
4.5.3
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2.1
5.2.2
5.2.3
5.2.4
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
6.2.15
Network Protocol ............................................................................................................................... 11
Data Rates......................................................................................................................................... 11
Network Reconfiguration ................................................................................................................... 12
Broadcast Messages......................................................................................................................... 13
Extended Timeout Function .............................................................................................................. 13
Line Protocol ..................................................................................................................................... 13
Microcontroller Interface.................................................................................................................... 16
Transmission Media Interface ........................................................................................................... 26
Microsequencer................................................................................................................................. 30
Internal Registers .............................................................................................................................. 32
Internal RAM ..................................................................................................................................... 46
Selecting Clock Frequencies Above 2.5 Mbps .......................................................................................11
Response Time.......................................................................................................................................13
Idle Time.................................................................................................................................................13
Reconfiguration Time..............................................................................................................................13
Invitations To Transmit ...........................................................................................................................14
Free Buffer Enquiries..............................................................................................................................14
Data Packets ..........................................................................................................................................14
Acknowledgements.................................................................................................................................15
Negative Acknowledgements .................................................................................................................15
Selection of 8/16-Bit Access ...................................................................................................................19
DMA Transfers To And From Internal RAM ............................................................................................19
DMA Operation .......................................................................................................................................20
DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ............................................................24
DMA Data Transfer Sequence (Memory to I/O: Write A Packet) ............................................................24
High Speed CPU Bus Timing Support ....................................................................................................24
Traditional Hybrid Interface.....................................................................................................................26
Backplane Configuration.........................................................................................................................26
Differential Driver Configuration..............................................................................................................28
Programmable TXEN Polarity.................................................................................................................28
Interrupt Mask Register (IMR) ................................................................................................................32
Data Register..........................................................................................................................................32
Tentative ID Register ..............................................................................................................................32
Node ID Register ....................................................................................................................................33
Next ID Register .....................................................................................................................................33
Status Register .......................................................................................................................................33
Diagnostic Status Register .....................................................................................................................33
Command Register.................................................................................................................................34
Address Pointer Registers ......................................................................................................................34
General Description ............................................................................................................. 6
Pin Configuration................................................................................................................. 7
Description of Pin Functions ............................................................................................... 8
Protocol Description........................................................................................................... 11
System Description............................................................................................................. 16
Functional Description....................................................................................................... 30
Configuration Register ........................................................................................................................34
Sub-Address Register .........................................................................................................................34
Setup 1 Register .................................................................................................................................34
Setup 2 Register .................................................................................................................................34
Bus Control Register ...........................................................................................................................35
DMA Count Register ...........................................................................................................................36
TABLE OF CONTENTS
DATASHEET
Page 3
Revision 02-27-06