COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 82

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 02-27-06
Internal Setting Pulse
Internal Setting Pulse
The EF bit also controls the resolution of the following issues from the COM20020 Rev B:
a)
b)
Network MAP Generation
Tentative ID is used for generating the Network MAP, but it sometimes detects a non-existent node.
Every time the Tentative-ID register is written, the effect of the old Tentative-ID remains active for a
while, which results in an incorrect network map. It can be avoided by a carefully coded software
routine, but this requires the programmer to have deep knowledge of how the COM20022I 3V works.
Duplicate-ID is mainly used for generating the Network MAP. This has the same issue as Tentative-
ID.
A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID,
when the COM20022I 3V detects a write operation to Tentative-ID or Node-ID register. With this
change, programmers can use the Tentative-ID or Duplicate-ID for generating the network MAP
without any issues. This change is Enabled/Disabled by the EF bit.
Mask Register Reset
The Mask register is reset by a soft reset in the COM20020 Rev. A, but is not reset in Rev. B. The
Mask register is related to the Status and Diagnostic register, so it should be reset by a soft reset.
Otherwise, every time the soft reset happens, the COM20020 Rev. B generates an unnecessary
interrupt since the status bits RI and TA are back to one by the soft reset.
This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft
reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to
High in the Configuration register. This solution is Enabled/Disabled by the EF bit.
nINTR pin
nINTR pin
EF=1
TA/RI bit
TA/RI bit
EF=0
Figure 9.1 -
Effect of the EF Bit on the TA/RI Bit
DATASHEET
Page 82
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
prohibition period
Tx/Rx completed
Tx/Rx completed
SMSC COM20022I 3V
Datasheet