COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 36

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.15 DMA Count Register
Revision 02-27-06
BIT
6,5 (Reserved)
7
4
3
2
1
The use of the TC8/RSYN/GTTM bit is also transfer mode dependent. TC8 is bit 8 of the Terminal Count
register. RSYN is the refresh synchronous bit; it is used to select whether the DMA is started immediately
or after Refresh execution. GTTM is the Gate Time bit; it is used to select the gate time of the
Programmable-Burst transfer.
TC8 is for Non-Burst or Burst mode. RSYN and GTTM are for the two Programmable-Burst modes.
The W16 bit is used to enable/disable the 16 bit access.
The DMA COUNT Register is new to the COM20022I 3V. It is an 8-bit read/write register accessed when
the Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address
Register). This register contains bits for control of the DMA functionality. The TC7-TC0 /TIM7-TIM0 /CYC7-
CYC0 bits have one of three functions depending on the DMA transfer mode. TC7-TC0 are for Non-Burst
or Burst mode. These are the lower 8 bits of the Terminal Count setting register (the MSB is in the Bus
Control Register). The TIM7-TIM0 bits are for setting the time of the continuous DMA transfer in
Programmable-Burst by Timer mode. The CYC7-CYC0 bits are for setting the cycle count value of the
continuous DMA transfer in Programmable-Burst by cycle mode.
Receiver
Inhibited
Power On Reset POR
Test
Reconfiguration
Transmitter
Message
Acknowledged
BIT NAME
SYMBOL
RI
TEST
RECON
TMA
This bit, if high, indicates that the receiver is not enabled because
either an "Enable Receive to Page fnn" command was never
issued, or a packet has been deposited into the RAM buffer page
fnn as specified by the last "Enable Receive to Page fnn"
command. No messages will be received until this command is
issued, and once the message has been received, the RI bit is
set, thereby inhibiting the receiver. The RI bit is cleared by
issuing an "Enable Receive to Page fnn" command. This bit,
when set, will cause an interrupt if the corresponding bit of the
Interrupt Mask Register (IMR) is also set. When this bit is set and
another station attempts to send a packet to this station, this
station will send a NAK.
These bits are undefined.
This bit, if high, indicates that the COM20022I 3V has been reset
by either a software reset, a hardware reset, or writing 00H to the
Node ID Register. The POR bit is cleared by the "Clear Flags"
command.
This bit is intended for test and diagnostic purposes. It is a logic
"0" under normal operating conditions.
This bit, if high, indicates that the Line Idle Timer has timed out
because the RXIN pin was idle for 20.5 S. The RECON bit is
cleared during a "Clear Flags" command. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
The interrupt service routine should consist of examining the
MYRECON bit of the Diagnostic Status Register to determine
whether there are consecutive reconfigurations caused by this
node.
This bit, if high, indicates that the packet transmitted as a result of
an "Enable Transmit from Page fnn" command has been
acknowledged. This bit should only be considered valid after the
TA bit (bit 0) is set. Broadcast messages are never
acknowledged. The TMA bit is cleared by issuing the "Enable
Transmit from Page fnn" command.
Table 6.5 - Status Register
DATASHEET
Page 36
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
DESCRIPTION
SMSC COM20022I 3V
Datasheet