COM20019ILJPTR SMSC, COM20019ILJPTR Datasheet - Page 24

• Manufacturer Part Number: COM20019ILJPTR
• Description: Network Controller & Processor ICs Arcnet (ANSI 878.1) Controllr 2k x 8 Ram
• Manufacturer: SMSC

Specifications of COM20019ILJPTR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDR
6.2
6.2.1
6.2.2
Rev. 09-25-07
07-0
07-1
07-2
07-3
07-4
00
01
02
03
04
05
06
RESET
RI/TR1
RBUS-
MODE
DATA
INTERNAL REGISTERS
The COM20019I contains 14 internal registers. Tables 2 and 3 illustrate the COM20019I register map. All
undefined bits are read as undefined and must be written as logic "0".
Interrupt Mask Register (IMR)
The COM20019I is capable of generating an interrupt signal when certain status bits become true. A write
to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR
are in the same position as their corresponding status bits in the Status Register and Diagnostic Status
Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits capable of
generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
New Next ID interrupt is cleared by reading the Next ID Register. The Interrupt Mask Register defaults to
the value 0000 0000 upon hardware reset.
Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes.
The data is placed in or retrieved from the address location presently specified by the address pointer.
The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the
NID7
MSB
TID7
TMG
RD-
P1-
C7
A7
D7
0
0
CCHEN
AUTO-
FOUR
NAKS
NID6
TID6
INC
C6
A6
D6
0
0
0
0
TXEN
TID5
NID5
C5
D5
A5
0
0
0
0
0
0
Table 6.2 - Write Register Summary
DATASHEET
RCV-
NID4
TID4
ET1
ALL
C4
A4
D4
0
0
0
0
0
WRITE
EXCNAK
Page 24
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
CKP3
TID3
NID3
ET2
C3
A3
D3
EF
0
0
0
SUB-AD2
RECON
PLANE
BACK-
SYNC
CKP2
TID2
NID2
NO-
A10
C2
D2
A2
0
NEXTID
CKP1
RCN-
NEW
SUB-
SUB-
TID1
NID1
AD1
AD1
TM1
C1
D1
A9
A1
0
SLOW-
RCN-
SUB-
SUB-
TID0
NID0
ARB
LSB
AD0
AD0
TM0
TTA
TA/
C0
D0
A8
A0
0
SMSC COM20019I
INTERRUPT
COMMAND
REGISTER
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
URATION
SUBADR
CONFIG-
NODEID
SETUP1
SETUP2
TENTID
MASK
DATA
TEST