COM20019ILJPTR SMSC, COM20019ILJPTR Datasheet - Page 3

• Manufacturer Part Number: COM20019ILJPTR
• Description: Network Controller & Processor ICs Arcnet (ANSI 878.1) Controllr 2k x 8 Ram
• Manufacturer: SMSC

Specifications of COM20019ILJPTR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE OF CONTENTS
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
SMSC COM20019I
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4.5.1
4.5.2
4.5.3
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
5.1.1
5.2.1
5.2.2
5.2.3
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
6.3.1
6.3.2
6.4.1
6.4.2
6.4.3
6.5.1
6.5.2
6.6.1
6.7.1
6.8.1
NETWORK PROTOCOL............................................................................................................................11
DATA RATES.............................................................................................................................................11
NETWORK RECONFIGURATION .............................................................................................................11
BROADCAST MESSAGES........................................................................................................................12
EXTENDED TIMEOUT FUNCTION ...........................................................................................................12
LINE PROTOCOL ......................................................................................................................................13
MICROCONTROLLER INTERFACE..........................................................................................................15
TRANSMISSION MEDIA INTERFACE ......................................................................................................19
MICROSEQUENCER.................................................................................................................................23
INTERNAL REGISTERS............................................................................................................................24
INTERNAL RAM ........................................................................................................................................35
SOFTWARE INTERFACE..........................................................................................................................35
COMMAND CHAINING..............................................................................................................................39
RESET DETAILS .......................................................................................................................................41
INITIALIZATION SEQUENCE ....................................................................................................................41
IMPROVED DIAGNOSTICS ......................................................................................................................42
GENERAL DESCRIPTION..................................................................................................... 5
PIN CONFIGURATIONS........................................................................................................ 6
DESCRIPTION OF PIN FUNCTIONS.................................................................................... 8
PROTOCOL DESCRIPTION ............................................................................................... 11
Response Time ...................................................................................................................................12
Idle Time .............................................................................................................................................12
Reconfiguration Time ..........................................................................................................................13
Invitations To Transmit........................................................................................................................13
Free Buffer Enquiries ..........................................................................................................................13
Data Packets.......................................................................................................................................13
Acknowledgements .............................................................................................................................14
Negative Acknowledgements ..............................................................................................................14
SYSTEM DESCRIPTION ..................................................................................................... 15
High Speed CPU Bus Timing Support ................................................................................................18
Backplane Configuration .....................................................................................................................19
Differential Driver Configuration ..........................................................................................................20
Programmable TXEN Polarity .............................................................................................................20
FUNCTIONAL DESCRIPTION............................................................................................. 23
Interrupt Mask Register (IMR) .............................................................................................................24
Data Register ......................................................................................................................................24
Tentative ID Register ..........................................................................................................................25
Node ID Register.................................................................................................................................25
Next ID Register..................................................................................................................................25
Status Register....................................................................................................................................25
Diagnostic Status Register ..................................................................................................................26
Command Register .............................................................................................................................26
Address Pointer Registers ..................................................................................................................26
Sequential Access Memory.................................................................................................................35
Access Speed .....................................................................................................................................35
Selecting RAM Page Size ...................................................................................................................36
Transmit Sequence .............................................................................................................................37
Receive Sequence ..............................................................................................................................38
Transmit Command Chaining .............................................................................................................40
Receive Command Chaining ..............................................................................................................40
Internal Reset Logic ............................................................................................................................41
Bus Determination...............................................................................................................................41
Normal Results:...................................................................................................................................43
Configuration Register.....................................................................................................................26
Sub-Address Register .....................................................................................................................26
Setup 1 Register..............................................................................................................................26
Setup 2 Register..............................................................................................................................27
DATASHEET
Page 3
Rev. 09-25-07