COM20019ILJPTR SMSC, COM20019ILJPTR Datasheet - Page 52
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COM20019ILJPTR
Manufacturer Part Number
COM20019ILJPTR
Description
Network Controller & Processor ICs Arcnet (ANSI 878.1) Controllr 2k x 8 Ram
Manufacturer
SMSC
Datasheet
1.COM20019I-DZD.pdf
(65 pages)
Specifications of COM20019ILJPTR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 52 of 65
- Download datasheet (387Kb)
Rev. 09-25-07
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
A0-A2
D0-D7
nCS
nWR
nRD
**
*
**
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
T
T
T
T
t10
ARB
ARB
ARB
opr
nCS may become active after control becomes active, but the access time (t6)
will now be 45nS measured from the leading edge of nCS.
t7
t8
t9
t1
t2
t3
t4
t5
t6
is the period of operation clock. Same as the XTAL1 period.
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Data Register requires a minimum of 5T
leading edge of the next nRD.
Data Register requires a minimum of 5T
leading edge of nRD.
nRD Low Width
nRD High Width
nWR
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
opr
if SLOW ARB = 1
to nRD Low
Note 3
opr
t1
t10
if SLOW ARB = 0
DATASHEET
CASE 1: RBUSTMG bit = 0
t3
Parameter
Page 52
t6
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
VALID
ARB
ARB
from the trailing edge of nRD to the
from the trailing edge of nWR to the
t8
VALID DATA
t5
4T
min
15
10
ARB
60
20
20
5**
0
0
*
max
40**
20
t7
t2
t4
Note 2
t9
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SMSC COM20019I
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