NTB90N02 ON Semiconductor, NTB90N02 Datasheet - Page 5

• Manufacturer Part Number: NTB90N02
• Description: MOSFET N-CH 24V 90A D2PAK
• Manufacturer: ON Semiconductor

Specifications of NTB90N02

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 5.8 mOhm @ 90A, 10V
• Drain To Source Voltage (vdss): 24V
• Current - Continuous Drain (id) @ 25° C: 90A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 29nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 2120pF @ 20V
• Power - Max: 85W
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (2 leads + tab)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
rudimentary analysis of the drive circuit so that
resistive load, V
known as the plateau voltage, V
times may be approximated by the following:
where:
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
Switching behavior is most easily modeled and predicted
The published capacitance data is difficult to use for
During the rise and fall time interval when switching a
V
R
During the turn−on and turn−off delay times, gate current
The equations are:
G
GG
t d(on) + R G C iss In [V GG (V GG * V GSP )]
t d(off) + R G C iss In (V GG V GSP )
= the gate drive voltage, which varies from
= the gate drive resistance and Q
zero to V
are read from the gate charge curve.
t r + Q 2
t f + Q 2
GS
GG
remains virtually constant at a level
t + Q I G(AV)
R 2 V GSP
R 2 10(V GG * V GSP )
G(AV)
SGP
) can be made from a
. Therefore, rise and fall
2
and V
POWER MOSFET SWITCHING
NTB90N02, NTP90N02
GSP
http://onsemi.com
5
at a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex.
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The capacitance (C
At high switching speeds, parasitic circuit elements
The resistive switching time variation versus gate
d(on)
The
and is read at a voltage corresponding to the
MOSFET
iss
) is read from the capacitance curve
d(off)
output
.
capacitance
also