AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 10

• Manufacturer Part Number: AT84CS001VTPY
• Description: Demultiplexer 240-Pin EBGA
• Manufacturer: E2V

Specifications of AT84CS001VTPY

• Package: 240EBGA
• Power Supply Type: Analog|Digital
• Typical Supply Current: 600 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 2.375|3.15 V
• Maximum Operating Supply Voltage: 2.625|3.45 V

Figure 3-9.
3.6
10
Asynchronous Reset (ASYNCRST)
0809E–BDC–05/09
(in DR/2 mode)
DRD (DORN)
in DR/2 mode
in DR/2 mode
in DR/2 mode
in DR/2 mode
DRC (CORN)
DRC (CORN)
DRD (DORN)
DRA (AORN)
DRB (BORN)
DRA (AORN)
DRB (BORN)
in DR mode
in DR mode
in DR mode
Staggered Mode in 1:4 Ratio (STAGG = 0)
in DR mode
in DR mode
Data Out
Data Out
Data Out
Data Out
The ASYNCRST asynchronous reset input is required to start/initialize the device, and acts as master
reset of the DMUX.
ASYNCRST is activated on logic HIGH (tied/switched to V
ing), and deactivated on logic LOW (grounded).
During the asynchronous reset, the DMUX’ differential clock input (CLK, CLKN) should be stopped at
low level (state in which e2v’s single ADC Data Ready signals are when the ADC is in reset mode).
The ASYNCRST pulse should last at least 1 ns. For ASYNCRST to CLK timing see
20.
Port A
Port B
Port D
Port C
DR
DR
N - 2
N - 1
N
N + 1
N + 2
N + 3
CCD
N + 4
= 3.3V, or 10 KΩ to ground, or left float-
N + 5
N + 6
e2v semiconductors SAS 2009
AT84CS001
Figure 4-1 on page