AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 32

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AT84CS001VTPY

Manufacturer Part Number
AT84CS001VTPY
Description
Demultiplexer 240-Pin EBGA
Manufacturer
E2V
Datasheet

Specifications of AT84CS001VTPY

Package
240EBGA
Power Supply Type
Analog|Digital
Typical Supply Current
600 mA
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
2.375|3.15 V
Maximum Operating Supply Voltage
2.625|3.45 V
8.2
Figure 8-3.
8.3
Figure 8-4.
32
LVDS Input Implementation
LVDS Output Implementation
0809E–BDC–05/09
AT84CS001 LVDS Input Data and Clock Termination Scheme
AT84CS001 LVDS Output Termination Scheme
The input data (I0, I0N...I9, I9N and IOR, IORN) and clock (CLK, CLKN) as well as the (DAI, DAIN) input
data of the standalone delay cell are LVDS-compatible. They are 2 × 50Ω differentially terminated as
shown in
The data (AI, AIN…DI, DIN, AOR/DRAN, AORN/DRA…DOR/DRDN, DORN/DRD and DAO/DAON) and
clock outputs (DR, DRN) are LVDS compatible. They must be 100Ω differentially terminated as shown in
Figure
8-4.
AT84CS001
Figure
8-3.
50Ω
50Ω
50Ω line
50Ω line
50Ω
50Ω
100Ω
AT84CS001
5 pF
Data or clock
inverted phase signal
Data or clock
in-phase signal
Positive output signal
Negative output signal
e2v semiconductors SAS 2009
AT84CS001

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