AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 19

• Manufacturer Part Number: AT84CS001VTPY
• Description: Demultiplexer 240-Pin EBGA
• Manufacturer: E2V

Specifications of AT84CS001VTPY

• Package: 240EBGA
• Power Supply Type: Analog|Digital
• Typical Supply Current: 600 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 2.375|3.15 V
• Maximum Operating Supply Voltage: 2.625|3.45 V

Table 4-4.
Notes:
e2v semiconductors SAS 2009
Parameter
Output Data Pipeline delay
Synchronized 1:2 mode
Synchronized 1:4 mode
Staggered 1:2 mode
Staggered 1:4 mode
Asynchronous Reset
ASYNCRST minimum pulse width
CLK to ASYNCRST timing
Forbidden area width
Minimum delay between falling edge of
ASYNCRST and rising edge of CLK
Standalone Delay Cell
Maximum Input Frequency
Input duty cycle
(DAI, DAIN) to (DAO, DAON) propagation delay
with DACTRL = V
(DAI, DAIN) to (DAO, DAON) propagation delay
with DACTRL = 2*V
SDA tuning range
1. Input data to input clock setup and hold time are not defined, because they are dependent of CLKDACTRL adjustment. It is
2. See
3. See Transfer characteristic on
4. The delay cell used in both standalone delay cell and Input clock path, has a characteristics that is not linear with Junction
recommended to center the clock edge in the middle of the data (with ± 100 ps) and to adjust CLKDACTRL depending on
clock sampling rate.
temperature. The largest tuning range is obtained near ambient temperature. See
Switching Performances and Characteristics (Continued)
Figure 4-1 on page
CCD
(4)
CCD
/3
/3
(3)
(2)
20, CLK to ASYNCRST timing is given assuming V (CLKDACLTRL) = V
Figure 3-11 on page
(3)
(3)
SDARANGE
DCYCSDA
TSDAMAX
TSDAMIN
Symbol
RSTPW
FMSDA
TPD
12.
Level
Test
4
5
4
4
4
4
4
4
4
1.70
2.20
Min
600
400
40
Figure 3-12 on page
0/0.5 /1/1.5
0/0.5
2.00
2.50
Typ
550
0.5
1.5
50
1
CC
/2
0809E–BDC–05/09
± 125
AT84CS001
Max
2.30
2.80
250
600
60
13.
Cycles
Clock
MHz
Unit
ns
ps
ps
ns
ns
ps
%
19