LAN9303-ABZJ Standard Microsystem (Smsc), LAN9303-ABZJ Datasheet - Page 113

• Manufacturer Part Number: LAN9303-ABZJ
• Description: Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9303-ABZJ

• Package: 56QFN EP
• Phy/transceiver Interface: MII/RMII
• Number Of Primary Switch Ports: 3
• Maximum Data Rate: 100 Mbps
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.19(Typ) A

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
8.4
8.4.1
EEPROM ADDRESS
14 and above
8 - 11
12
13
0
1
2
3
4
5
6
7
The EEPROM Loader interfaces to the I
(via the Register Access MUX). All system CSRs are accessible to the EEPROM Loader.
The EEPROM Loader runs upon a pin reset (nRST), power-on reset (POR), digital reset
(DIGITAL_RST)
command via the
page 42
The EEPROM contents must be loaded in a specific format for use with the EEPROM Loader. An
overview of the EEPROM content format is shown in
discussed in detail in the following sections.
EEPROM Loader Operation
Upon a pin reset (nRST), power-on reset (POR), digital reset
Reset Control Register
EEPROM Command Register
EEPROM Command Register (E2P_CMD)
Ready (READY)
device should be attempted. The operational flow of the EEPROM Loader can be seen in
EEPROM Loader
for additional information on resets.
EEPROM Valid Flag
MAC Address Low Word [7:0]
MAC Address Low Word [15:8]
MAC Address Low Word [23:16]
MAC Address Low Word [31:24]
MAC Address High Word [7:0]
MAC Address High Word [15:8]
Configuration Strap Values Valid Flag
Configuration Strap Values
Burst Sequence Valid Flag
Number of Bursts
Burst Data
bit in the
bit of the
Table 8.2 EEPROM Contents Format Overview
EEPROM Command Register
(RESET_CTL)), or upon the issuance of a RELOAD command via the
Reset Control Register
Hardware Configuration Register (HW_CFG)
(E2P_CMD), the
DESCRIPTION
DATASHEET
2
C EEPROM controller, the PHYs, and to the system CSRs
113
will be set. While the EEPROM Loader is active, the
(RESET_CTL)), or upon the issuance of a RELOAD
EEPROM Controller Busy (EPC_BUSY)
(E2P_CMD). Refer to
Table
8.2. Each section of EEPROM contents is
(Digital Reset (DIGITAL_RST)
See
See
is cleared and no writes to the
2
1
3
4
5
6
nd
rd
st
th
th
th
Section 4.2, "Resets," on
Section 8.4.5, "Register
Section 8.4.5, "Register
Byte on the Network
Byte on the Network
Byte on the Network
Byte on the Network
Byte on the Network
Byte on the Network
See
Revision 1.4 (07-07-10)
VALUE
Data"
Data"
Table 8.3
A5h
A5h
A5h
(Digital Reset
Figure
bit in the
bit in the
Device
8.7.