LAN9303-ABZJ Standard Microsystem (Smsc), LAN9303-ABZJ Datasheet - Page 244

• Manufacturer Part Number: LAN9303-ABZJ
• Description: Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9303-ABZJ

• Package: 56QFN EP
• Phy/transceiver Interface: MII/RMII
• Number Of Primary Switch Ports: 3
• Maximum Data Rate: 100 Mbps
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.19(Typ) A

Revision 1.4 (07-07-10)
13.4.2.18
BITS
31:0
RX Alignment
Count of packets that have between 64 bytes and the maximum allowable
number of bytes and are not byte aligned and have a bad FCS. The max
number of bytes is 1518 for untagged packets and 1522 for tagged packets.
If the
(MAC_RX_CFG_x), the max number of bytes is 2048.
Note:
Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x)
This register provides a counter of received packets with 64 bytes to the maximum allowable, and a
FCS error. The counter is cleared upon being read.
Note: For this counter, a packet with the maximum number of bytes that is not an integral number of
Jumbo2K
This counter will stop at its maximum value of FFFF_FFFFh.
Minimum rollover time at 100Mbps is approximately 481 hours.
bytes (e.g. a 1518 1/2 byte packet) and a FCS error is considered an alignment error and is
counted.
Register #:
bit is set in the
Port0: 041Fh
Port1: 081Fh
Port2: 0C1Fh
DESCRIPTION
Port x MAC Receive Configuration Register
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
244
Size:
32 bits
TYPE
SMSC LAN9303/LAN9303i
RC
00000000h
DEFAULT
Datasheet